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HC05CJ4GRS/d rev 2.1 68hc05cj4 68hc705cj4 specification (general release) january 3, 1996 csic mcu section sendai design operations nippon motorola ltd. sendai 981-32 japan motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part.
mc68hc(7)05cj4 motorola rev. 2.1 iii table of contents paragraph title page section 1 general description 1.1 introduction ................................................................................................... 1-1 1.2 features ........................................................................................................ 1-1 1.3 mask options ................................................................................................ 1-4 1.4 signal description ......................................................................................... 1-4 1.4.1 v dd and v ss ........................................................................................... 1-4 1.4.2 reset .................................................................................................... 1-4 1.4.3 maskable interrupt request ( irq) .......................................................... 1-5 1.4.4 osc1 and osc2 .................................................................................... 1-5 1.4.5 tcap and tcmp .................................................................................... 1-5 1.4.6 pa0 through pa7 .................................................................................... 1-5 1.4.7 pb0 through pb7 .................................................................................... 1-6 1.4.8 pc0 through pc7 ................................................................................... 1-6 1.4.9 pd0 through pd7 ................................................................................... 1-6 section 2 memory 2.1 introduction ................................................................................................... 2-1 2.2 summary of internal registers and i/o map ................................................. 2-2 2.3 ram .............................................................................................................. 2-5 2.4 self-check rom (mc68hc05cj4) .............................................................. 2-5 2.5 boot rom (mc68hc705cj4) ....................................................................... 2-5 2.6 mask rom (mc68hc05cj4) ....................................................................... 2-5 2.7 eprom/otp (mc68hc705cj4) .................................................................. 2-5 section 3 cpu core 3.1 introduction ................................................................................................... 3-1 3.2 accumulator (a) ............................................................................................ 3-1 3.3 index register (x) ......................................................................................... 3-1 3.4 program counter (pc) .................................................................................. 3-2 3.4.1 stack pointer (sp) .................................................................................. 3-2 3.4.2 condition code register (ccr) ............................................................. 3-3
motorola mc68hc(7)05cj4 iv rev. 2.1 table of contents paragraph title page section 4 interrupts 4.1 introduction ................................................................................................... 4-1 4.2 hardware controlled interrupt sequence ..................................................... 4-2 4.3 software interrupt (swi) ............................................................................... 4-3 4.4 external interrupt .......................................................................................... 4-3 4.5 timer 1 interrupt ........................................................................................... 4-3 4.6 sci interrupt .................................................................................................. 4-3 4.7 spi interrupt .................................................................................................. 4-4 4.8 i2c interrupt .................................................................................................. 4-4 4.9 timer 2 interrupt ........................................................................................... 4-4 section 5 resets 5.1 introduction ................................................................................................... 5-1 5.2 power-on reset (por) ................................................................................ 5-1 5.3 reset pin .................................................................................................... 5-1 5.4 computer operating properly (cop) reset ................................................. 5-1 section 6 modes of operation 6.1 introduction ................................................................................................... 6-1 6.2 mode entry .................................................................................................... 6-1 6.3 single-chip mode (scm) .............................................................................. 6-2 6.4 self-check/bootstrap mode .......................................................................... 6-2 6.5 low-power modes ........................................................................................ 6-2 6.5.1 stop mode .............................................................................................. 6-3 6.5.2 stop recovery ........................................................................................ 6-3 6.5.3 wait mode .............................................................................................. 6-3 section 7 input/output ports 7.1 introduction ................................................................................................... 7-1 7.2 port a ............................................................................................................ 7-1 7.3 port b ............................................................................................................ 7-1 7.4 port c ............................................................................................................ 7-1 7.5 port d ............................................................................................................ 7-2 7.6 input/output programming ............................................................................ 7-2
mc68hc(7)05cj4 motorola rev. 2.1 v table of contents paragraph title page section 8 serial communications interface 8.1 introduction ................................................................................................... 8-1 8.2 transmit operation ....................................................................................... 8-1 8.3 receive operation ........................................................................................ 8-3 8.3.1 receiver front end ................................................................................. 8-3 8.3.2 receiver functional operation ............................................................. 8-10 8.3.3 idle line detect ..................................................................................... 8-12 8.3.4 receiver wakeup ................................................................................. 8-12 8.3.5 idle line wakeup .................................................................................. 8-13 8.3.6 address mark wakeup ......................................................................... 8-13 8.4 sci register descriptions ........................................................................... 8-14 8.4.1 sci baud rate control register ........................................................... 8-14 8.4.2 sci control register 1 (sccr1) .......................................................... 8-16 8.4.3 sci control register 2 (sccr2) .......................................................... 8-17 8.4.4 sci status register (scsr) ................................................................. 8-18 8.4.5 sci data register (scdr) ................................................................... 8-20 section 9 serial peripheral interface 9.1 introduction ................................................................................................... 9-1 9.2 signal description ......................................................................................... 9-1 9.2.1 master in slave out (miso) ................................................................... 9-1 9.2.2 serial data in (mosi) ............................................................................. 9-2 9.2.3 serial clock in/out (sck1) ..................................................................... 9-2 9.2.4 slave select (ss) ................................................................................... 9-3 9.3 spi registers ................................................................................................ 9-4 9.3.1 spi control register (spcr) ................................................................. 9-4 9.3.2 spi status register (spsr) ................................................................... 9-7 9.3.3 spi data register (spdr) ..................................................................... 9-8 section 10 slave-only m-bus 10.1 introduction ................................................................................................. 10-1 10.2 operation of somb and ninth-bit detector ................................................ 10-1 10.2.1 after reset ............................................................................................ 10-1 10.2.2 first reception ..................................................................................... 10-1 10.2.3 after the first reception ....................................................................... 10-2 10.2.4 subsequent receptions ....................................................................... 10-3 10.2.5 acknowledgment .................................................................................. 10-3
motorola mc68hc(7)05cj4 vi rev. 2.1 table of contents paragraph title page 10.2.6 stop condition ...................................................................................... 10-3 10.2.7 general call address detect ................................................................ 10-3 10.3 slave m-bus control register (mbcr) ....................................................... 10-4 10.4 slave m-bus status register (mbsr) ........................................................ 10-6 10.5 m-bus address/data register (mbadr) .................................................... 10-7 10.6 hardware flowchart of the somb .............................................................. 10-8 10.7 somb timing diagrams ........................................................................... 10-10 section 11 timer 1 11.1 introduction ................................................................................................. 11-1 11.2 counter ....................................................................................................... 11-2 11.3 output compare register ........................................................................... 11-3 11.4 input capture register ................................................................................ 11-4 11.5 timer 1 control register (t1cr) ................................................................ 11-6 11.6 timer 1 status register (t1sr) .................................................................. 11-7 11.7 timer 1 during wait mode .......................................................................... 11-8 11.8 timer 1 during stop mode .......................................................................... 11-8 section 12 timer 2 12.1 introduction ................................................................................................. 12-1 12.2 flag clearing considerations ...................................................................... 12-2 12.2.1 clearing timer overflow flag (tof) .................................................... 12-3 12.2.2 clearing timer overflow flag enable (tofe) ...................................... 12-3 12.3 timer 2 control and status register (t2csr) ........................................... 12-4 12.4 cop watchdog reset ................................................................................. 12-6 12.5 timer 2 counter register (t2cr) ............................................................... 12-6 12.6 timer 2 during wait mode .......................................................................... 12-6 12.7 timer 2 during stop mode .......................................................................... 12-6 section 13 instruction set 13.1 introduction ................................................................................................. 13-1 13.2 addressing modes ...................................................................................... 13-1 13.2.1 inherent ................................................................................................ 13-1 13.2.2 immediate ............................................................................................. 13-1 13.2.3 direct .................................................................................................... 13-2 13.2.4 extended .............................................................................................. 13-2 13.2.5 indexed, no offset ................................................................................ 13-2
mc68hc(7)05cj4 motorola rev. 2.1 vii table of contents paragraph title page 13.2.6 indexed, 8-bit offset ............................................................................. 13-2 13.2.7 indexed, 16-bit offset ........................................................................... 13-3 13.2.8 relative ................................................................................................. 13-3 13.3 instruction types ......................................................................................... 13-4 13.3.1 register/memory instructions ............................................................... 13-4 13.3.2 read-modify-write instructions ............................................................ 13-5 13.3.3 jump/branch instructions ..................................................................... 13-5 13.3.4 bit manipulation instructions ................................................................. 13-7 13.3.5 control instructions ............................................................................... 13-7 13.4 instruction set summary ............................................................................. 13-8 section 14 electrical specifications 14.1 introduction ................................................................................................. 14-1 14.2 maximum ratings ....................................................................................... 14-1 14.3 operating temperature range ................................................................... 14-2 14.4 thermal characteristics .............................................................................. 14-2 14.5 power considerations ................................................................................. 14-2 14.6 recommended dc operating characteristics ............................................ 14-3 14.7 dc electrical characteristics (4.5 to 5.5 vdc) ............................................. 14-3 14.8 dc electrical characteristics (3.0 to 4.5 vdc) ............................................. 14-4 14.9 control timing (4.5 to 5.5 vdc) ................................................................... 14-5 14.10 control timing (3.0 to 4.5 vdc) ................................................................... 14-5 section 15 mechanical specifications 15.1 introduction ................................................................................................. 15-1 15.2 44-lead qfp package (case 824-e) ......................................................... 15-2 section 16 ordering information 16.1 introduction ................................................................................................. 16-1 16.2 mcu ordering forms .................................................................................. 16-1 16.3 application program media ......................................................................... 16-1 16.4 rom program verification .......................................................................... 16-2 16.5 rom verification units (rvus) ................................................................... 16-3 16.6 mc order numbers ..................................................................................... 16-3
mc68hc(7)05cj4 motorola rev. 2.1 ix list of figures figure title page 1-1 block diagram ............................................................................................... 1-2 1-2 memory map ................................................................................................. 1-3 1-3 pin assignment for single-chip mode (44-lead qfp package) .................. 1-4 2-1 mc68hc(7)05cj4 memory map .................................................................. 2-1 2-2 register description key .............................................................................. 2-2 2-3 i/o map ($0000:$000f) ................................................................................. 2-3 2-4 i/o map ($0010:$001f) ................................................................................. 2-4 3-1 programming model ...................................................................................... 3-1 3-2 stacking order .............................................................................................. 3-2 4-1 interrupt flowchart ........................................................................................ 4-5 5-1 power-on reset and reset ....................................................................... 5-2 6-1 mc68hc(7)05cj4 mode entry diagram ...................................................... 6-2 6-2 stop recovery timing diagram .................................................................... 6-3 6-3 stop/wait mode flowcharts .......................................................................... 6-4 7-1 i/o circuitry ................................................................................................... 7-3 8-1 start search example 1 ................................................................................ 8-6 8-2 start search example 2 ................................................................................ 8-6 8-3 start search example 3 ................................................................................ 8-7 8-4 start search example 4 ................................................................................ 8-7 8-5 start search example 5 ................................................................................ 8-8 8-6 start search example 6 ................................................................................ 8-8 8-7 start search example 7 ................................................................................ 8-9 8-8 sci baud rate control register ................................................................. 8-14 8-9 sci control register 1 ................................................................................ 8-16 8-10 sci control register 2 ................................................................................ 8-17 8-11 sci status register .................................................................................... 8-18 8-12 sci data register ....................................................................................... 8-20 9-1 spi control register ..................................................................................... 9-4 9-2 spi clock/data relationships ....................................................................... 9-6 9-3 spi status register ....................................................................................... 9-7 9-4 spi control register ..................................................................................... 9-8
motorola mc68hc(7)05cj4 x rev. 2.1 list of figures figure title page 10-1 m-bus control register ............................................................................... 10-4 10-2 m-bus status register ................................................................................ 10-6 10-3 m-bus address/data register .................................................................... 10-7 10-4 m-bus data address/register .................................................................... 10-7 10-5 somb flowchart ......................................................................................... 10-8 10-6 first reception timing .............................................................................. 10-10 10-7 additional receptions timing ................................................................... 10-10 10-8 transmissions (master read) timing ....................................................... 10-11 11-1 timer 1 block diagram ............................................................................... 11-2 11-2 timer 1 output compare operation ........................................................... 11-3 11-3 timer 1 input capture operation ................................................................ 11-5 11-4 timer 1 control register ............................................................................. 11-6 11-5 timer 1 status register .............................................................................. 11-7 12-1 timer 2 block diagram ............................................................................... 12-2 12-2 timer 2 control/status register .................................................................. 12-4 12-3 timer 2 counter register ............................................................................ 12-6
mc68hc(7)05cj4 motorola rev. 2.1 xi list of tables table title page 4-1 vector address for interrupts and reset........................................................ 4-2 6-1 mode select summary................................................................................... 6-1 7-1 i/o pin functions ........................................................................................... 7-2 8-1 scp1:scp0 select ...................................................................................... 8-14 8-2 scr2:scr0 select...................................................................................... 8-15 9-1 spi clock rates............................................................................................. 9-5 12-1 rti and cop rates at 2 mhz bus frequency ............................................ 12-5 13-1 register/memory instructions ...................................................................... 13-4 13-2 read-modify-write instructions.................................................................... 13-5 13-3 jump and branch instructions ..................................................................... 13-6 13-4 bit manipulation instructions ........................................................................ 13-7 13-5 control instructions ...................................................................................... 13-7 13-6 instruction set summary.............................................................................. 13-8 13-7 opcode map .............................................................................................. 13-14 16-1 mc order numbers...................................................................................... 16-3
general release specification mc68hc(7)05cj4 general description motorola rev. 2.1 1-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 1 general description 1.1 introduction this mc68hc(7)05cj4 is a 44-pin microcontroller unit (mcu) with highly sophisticated on-chip peripheral functions. the memory map includes nearly 4 kbytes of user rom or eprom and 224 bytes of ram. the mcu has four ports: a, b, c, and d. ports a, b, and c are bidirectional, and port d is output only, supporting several multifunction pins. the mc68hc05cj4 has two timers, a cop watchdog, a serial peripheral interface (spi), a serial communications interface (sci), and a slave-only i 2 c bus. 1.2 features ? low cost ? m68hc05 core ? 44-lead quad flat pack (qfp) package ? 3856 bytes of user mask rom or eprom ? 224 bytes of on-chip ram ? 24 bidirectional i/o lines, 7 input-only lines ? 15-stage multifunctional timer ? 16-bit timer with input capture and output compare ? cop watchdog timer ? power saving stop mode/wait mode ? asynchronous serial communications interface (sci) ? synchronous serial peripheral interface (spi) ? slave only i 2 c bus (m-bus) ? port c has 10 ma-per-pin drive capability
general release specification motorola general description mc68hc(7)05cj4 1-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 1-1. block diagram 0 000000011 cpu control arithmetic/logic unit accumulator index register stack pointer 0 00 program counter m68hc05 mcu reset condition code register 111hi nzc data direction register a port a pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 timer 2/cop internal oscillator divide by two timer 1 irq v dd v ss osc1 osc2 user ram 224 x 8 reset data direction register b port b pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 data direction register c port c test rom 240 x 8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 system tcmp tcap system cpu clock power internal clock user rom 3856 x 8 pd7/sck2 pd6/sdio pd5/ ss pd4/sck1 pd3/mosi pd2/miso pd1/tdo pd0/rdi port d baud rate generator i 2 c sci spi internal clock
general release specification mc68hc(7)05cj4 general description motorola rev. 2.1 1-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 1-2 . memory map note a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. the exact values and their tolerance or limits are specified in section 14 electrical specifications. ram 224 bytes stack 64 bytes i/o 32 bytes $0020 $00c0 $0100 $1000 $0000 0000 0032 0192 0256 4096 $1f00 7936 user rom 3840 bytes unused 3840 bytes self-check rom 240 bytes self-check vectors user vectors 16 bytes $1fe0 $1ff0 $1fff 8176 8191 8160
general release specification motorola general description mc68hc(7)05cj4 1-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 1-3. pin assignment for single-chip mode (44-lead qfp package) 1.3 mask options stop disable is a mask programmable option on mc68hc05cj4. there are no mask programmable options on mc68hc705cj4. 1.4 signal description this section mainly describes signals in the single-chip mode or the user mode. see figure 1-3. 1.4.1 v dd and v ss the power is supplied to the microcontroller using v dd and v ss . v dd is the positive supply, and v ss is ground. for more detailed information refer to 14.6 dc operating characteristics . 1.4.2 reset this pin is used to reset the mcu and provide an orderly start-up procedure by pulling reset low. the reset and power-on reset (por) functions do not 28 33 pd6/sdio pd5/ ss pd4/sck1 pd3/mosi pd2/miso pd1/td0 pd0/rdi pc0 pc1 pc2 23 pc3 7 12 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 11 pb2 pb3 39 17 22 44 34 1 mc68hc(7)05cj4 44-pin qfp nc pa7 reset v dd osc1 osc2 tcap irq/v pp pd7/sck2 tcmp v ss nc pc4 pc5 pc6 pc7 v ss pb4 nc pb7 pb6 pb5
general release specification mc68hc(7)05cj4 general description motorola rev. 2.1 1-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 depend on the mcu operation modes and all pins are configured as single-chip mode pins while the reset pin is low. 1.4.3 maskable interrupt request ( irq) this pin has a programmable option that provides two different choices of interrupt triggering sensitivity. the options are: 1. negative edge-sensitive triggering only, or 2. both negative edge-sensitive and level-sensitive triggering. the mcu completes the current instruction before it responds to the interrupt request. when irq goes low for at least one t ilih , a logic one is latched internally to signify an interrupt has been requested. when the mcu completes its current instruction, the interrupt latch is tested. if the interrupt latch contains a logic one, and the interrupt mask bit (i bit) in the condition code register is clear, the mcu then begins the interrupt sequence. see section 4 interrupts for more information on irq programming. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for wire-or operation. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. on the mc68hc705cj4, this pin becomes irq/v pp and has the added function of providing the programming voltage for the on-board eprom. 1.4.4 osc1 and osc2 these pins provide control input for an on-chip clock oscillator circuit. a crystal or an external clock signal connects to these pins providing a system clock. 1.4.5 tcap and tcmp these two pins are associated with the 16-bit timer (timer 1). tcap is an input only to the input capture system, and tcmp is an output only from the output compare system. see section 11 timer 1 . 1.4.6 pa0 through pa7 port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $0000 and the data direction register (ddra) is at $0004. reset does not affect the data register, but clears the data direction register, thereby returning the port to inputs. writing a one to a ddra bit sets the corresponding port bit to output mode.
general release specification motorola general description mc68hc(7)05cj4 1-6 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1.4.7 pb0 through pb7 port b is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port b data register is at $0001 and the data direction register (ddrb) is at $0005. reset does not affect the data register, but clears the data direction register, thereby returning the port to inputs. writing a one to a ddrb bit sets the corresponding port bit to output mode. 1.4.8 pc0 through pc7 port c is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port c data register is at $0002 and the data direction register (ddrc) is at $0006. reset does not affect the data register, but clears the data direction register, thereby returning the port to inputs. writing a one to a ddrc bit sets the corresponding port bit to output mode. 1.4.9 pd0 through pd7 port d is an 8-bit input-only port. pd7:pd6 pins are shared with the i 2 c subsystem, pd5:pd2 are shared with the spi subsystem and pd1:pd0 are shared with the sci subsystem. the port d data register is at $0003 and there is no data direction register. reset does not affect the data register.
general release specification mc68hc(7)05cj4 memory motorola rev. 2.1 2-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 2 memory 2.1 introduction the mc68hc05cj4 contains 3840 mask rom, 240 bytes of self-check rom, and 224 bytes of ram. an additional 16 bytes of mask rom is provided for user vectors at $1ff0 through $1fff. in the mc68hc705cj4 (eprom device), rom and user vector areas are replaced by the eprom cell, and self-check rom becomes bootstrap rom. figure 2-1. mc68hc(7)05cj4 memory map $0000 $001f $0020 $00c0 $00ff $0100 $1000 $1f00 $1fdf $1fe0 $1fef $1ff0 $1fff ram 224 bytes stack 64 bytes 224 bytes unused reserved user vectors $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f port a data register port b data register port a data direction reg port b data direction reg port c data register port d data register port c data direction reg program control register timer counter register spi control register mbus control register timer control register timer status register output compare register (h) output compare register (l) input capture register (h) input capture register (l) timer counter (h) timer counter (l) alternate counter (h) alternate counter (l) mbus add and data register for eprom parts only mask rom 3840 bytes (eprom 3840 bytes) self-test rom (bootstrap rom) i/o 32 bytes timer status and control spi status register spi data register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register mbus status register reserved
general release specification motorola memory mc68hc(7)05cj4 2-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2.2 summary of internal registers and i/o map figure 2-2 explains how to interpret the register figures used in this document. figure 2-2. register description key b7 b6 b5 b4 b3 b2 b1 b0 bit 7 identifier bit name (mnemonic) register name register address icie $0012 ocie toie 0 0 0 iedg olvl xxxx 000000u0 reset: reset state or condition: (u = unaffected by reset) (* = reflects input pin state)
general release specification mc68hc(7)05cj4 memory motorola rev. 2.1 2-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 internal registers bit 7 654321 bit 0 $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa2 pa0 porta $0001 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb $0002 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 portd $0004 ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 ddra $0005 ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 ddrb $0006 ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 ddrc $0007 unused $0008 tof rtif tofe rtie irqs cope rt1 rt0 t2csr $0009 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t2cr $000a spie spe dod mstr cpol cpha spr1 spr0 spcr $000b spif wcol 0 modf 0000 spsr $000c spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr $000d 0 0 scp1 scp0 0 scr2 scr1 scr0 baud $000e r8 t8 0 m wake 0 0 0 sccr1 $000f tie tcie rie ilie te re rwu sbk sccr2 bit 7 654321 bit 0 figure 2-3. i/o map ($0000:$000f)
general release specification motorola memory mc68hc(7)05cj4 2-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 internal registers bit 7 654321 bit 0 $0010 tdre tc rdrf idle or nf fe 0 scsr $0011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scdr $0012 icie ocie toie 0 0 0 iedg olvl t1cr $0013 icf ocf tof 00000 t1sr $0014 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 icrh $0015 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 icrl $0016 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ocrh $0017 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ocrl $0018 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 trh $0019 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 trl $001a bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 atrh $001b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 atrl $001c adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 mbadr $001d smie sme t/r noack 0 0 0 clkr mbcr $001e smf srdf mack 00000 mbsr $001f bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 test bit 7 654321 bit 0 figure 2-4. i/o map ($0010:$001f)
general release specification mc68hc(7)05cj4 memory motorola rev. 2.1 2-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2.3 ram the 224-byte internal ram is positioned at $0020 through $00ff in the memory map. all of the memory is positioned in page zero and is accessible by direct addressing mode, but the upper 64 bytes of page zero are used for the cpu stack area. extreme caution should be taken if the stack area is used for data storage. the ram is implemented with static cells and retains its contents during the stop and wait modes. 2.4 self-check rom (mc68hc05cj4) self-check rom is the 240 bytes of mask rom positioned at $1f00 through $1fef. this rom contains self-check programs and reset/interrupt vectors in the self-check mode. 2.5 boot rom (mc68hc705cj4) boot rom is the 240 bytes of mask rom positioned at $1f00 through $1fef. this rom contains bootstrap programs and reset/interrupt vectors in the bootstrap mode. the programs include: ? eprom programming and verify ? dumping eprom contents ? reading program into the internal ram ? executing program in the internal ram 2.6 mask rom (mc68hc05cj4) the 3840-byte user rom is positioned at $1000 through $1eff, and additional 16-byte rom is located at $1ff0 through $1fff for user vectors. in this mask rom device, v pp pin is not used and program control register (pcr) is not implemented. 2.7 eprom/otp (mc68hc705cj4) the 3840-byte eprom is positioned at $1000 through $1eff, and additional 16-byte eprom is located at $1ff0 through $1fff for user vectors. the erased state of eprom is read as $ff and eprom power is supplied from v pp pin and v dd pin. the program control register (pcr) is provided for the eprom programming and testing. this register is only available in special test modes.
general release specification mc68hc(7)05cj4 cpu core motorola rev. 2.1 3-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 3 cpu core 3.1 introduction the mcu contains five registers as shown in the programming model of figure 3-1. this section describes these registers. figure 3-1. programming model 3.2 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.3 index register (x) the index register is an 8-bit register used for the indexed addressing value to create an effective address. the index register may also be used as a temporary storage area. h i n z c ccr sp 1 1 0 0 0 0 0 0 0 0 pc 0 0 0 12 15 7 0 0 program counter stack pointer condition code register 15 x 0 7 a 0 7 index register accumulator
general release specification motorola cpu core mc68hc(7)05cj4 3-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3.4 program counter (pc) the program counter is a 16-bit register that contains the address of the next byte to be fetched. 3.4.1 stack pointer (sp) the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the 10 most significant bits are permanently set to 0000000011. these 10 bits are appended to the six least significant bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. see figure 3-2 for more information. figure 3-2. stacking order note since the stack pointer decrements during pushes, the program counter low (pcl) is stacked first, followed by program counter high (pch), etc. pulling from the stack is in the reverse order. index register pcl accumulator condition code register pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing memory addresses memory addresses
general release specification mc68hc(7)05cj4 cpu core motorola rev. 2.1 3-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3.4.2 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be individually tested by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set, the hardware interrupts are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates.
general release specification mc68hc(7)05cj4 interrupts motorola rev. 2.1 4-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 4 interrupts 4.1 introduction the mcu can be interrupted seven different ways: the six maskable hardware interrupts ( irq, sci, spi, i 2 c, timer 1, and timer 2) and the non-maskable software interrupt instruction (swi). interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. note the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. the swi is executed the same as any other instruction, regardless of the i-bit state. see table 4-1 for more information.
general release specification motorola interrupts mc68hc(7)05cj4 4-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4.2 hardware controlled interrupt sequence the following three functions ( reset, stop, and wait) are not in the strictest sense an interrupt; however, they are acted upon in a similar manner. flowcharts for hardware interrupts are shown in figure 4-1 . a discussion is provided below. 1. reset a low input on the reset input pin causes the program to vector to its starting address which is specified by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register is also set. much of the mcu is configured to a known state during this type of reset. 2. stop the stop instruction causes the oscillator to be turned off and the processor to sleep until an external interrupt ( irq) or reset occurs. 3. wait the wait instruction causes all processor clocks to stop, but leaves the timer clocks running. this rest state of the processor can be cleared by reset, or any hardware interrupt. there are no special wait vectors for these individual interrupts. table 4-1. vector address for interrupts and reset register flag name interrupts cpu interrupt vector address n/a n/a reset reset $1ffeC$1fff n/a n/a software swi $1ffcC$1ffd n/a n/a external interrupt irq $1ffaC$1ffb tsr icf timer input capture timer 1 $1ff8C$1ff9 tsr ocf timer output compare timer 1 $1ff8C$1ff9 tsr tof1 timer 1 over?ow timer 1 $1ff8C$1ff9 scsr tdre transmit buffer empty sci $1ff6C$1ff7 scsr tc transmit complete sci $1ff6C$1ff7 scsr rdrf receiver buffer full sci $1ff6C$1ff7 scsr idle idle line detect sci $1ff6C$1ff7 scsr or overrun sci $1ff6C$1ff7 spsr spif transfer complete spi $1ff4C$1ff5 spsr modf mode fault spi $1ff4C$1ff5 mbsr smf slave m-bus flag iic $1ff2C$1ff3 tcsr tof2 timer 2 over?ow timer 2 $1ff0C$1ff1 tcsr rti real time interrupt timer 2 $1ff0C$1ff1
general release specification mc68hc(7)05cj4 interrupts motorola rev. 2.1 4-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt: it is executed regardless of the state of the i bit in the ccr. if the i bit is zero (interrupts enabled), swi executes after interrupts which were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. 4.4 external interrupt if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of irq. it is then synchronized internally and serviced as specified by the contents of $1ffa and $1ffb. either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger operation is selectable by writing to bit 3 of the t2csr register. note the internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i bit is cleared. 4.5 timer 1 interrupt there are three different timer interrupt flags that cause a timer interrupt whenever they are set and enabled. the interrupt flags are in the timer status register (tsr), and the enable bits are in the timer control register (tcr). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1ff8 and $1ff9. 4.6 sci interrupt there are five different sci interrupt flags that cause an sci interrupt whenever they are set and enabled. the interrupt flags are in the sci status register (scsr), and the enable bits are in the sci control register 2 (sccr2). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1ff6 and $1ff7.
general release specification motorola interrupts mc68hc(7)05cj4 4-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4.7 spi interrupt there are two different spi interrupt flags that cause an spi interrupt whenever they are set and enabled. the interrupt flags are in the spi status register (spsr), and the enable bits are in the spi control register (spcr). either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1ff4 and $1ff5. 4.8 i 2 c interrupt there is one i 2 c interrupt flag that causes an i 2 c interrupt whenever it is set and enabled. the interrupt flag is in the i 2 c status register (mbsr), and the enable bits are in the i 2 c control register (mbcr). this interrupt will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1ff2 and $1ff3. 4.9 timer 2 interrupt there are two different timer 2 interrupt flags that cause a timer interrupt whenever they are set and enabled. the interrupt flags and enables are in the timer status and control register (tcsr). either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1ff0 and $1ff1.
general release specification mc68hc(7)05cj4 interrupts motorola rev. 2.1 4-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 4-1. interrupt flowchart load pc from: swi: $1ffc-$1ffd irq: $1ffa-$1ffb timer 1: $1ff8-$1ff9 sci: $1ff6-$1ff7 spi: $1ff4-$1ff5 iic: $1ff2-$1ff3 timer 2: $1ff0-$1ff1 n y internal timer 2 interrupt n restore registers from stack: ccr, a, x, pc irq external interrupt set i bit in cc register stack pc, x, a, ccr clear irq request latch fetch next instruction execute instruction n n y y y n i bit in ccr set? internal spi interrupt swi instruction ? n y rti instruction ? y from reset n y internal timer 1 interrupt n y internal sci interrupt
general release specification mc68hc(7)05cj4 resets motorola rev. 2.1 5-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 5 resets 5.1 introduction the mcu can be reset two ways: by the initial power-on reset function or by an active low input to the reset pin. see figure 5-1. 5.2 power-on reset (por) an internal reset is generated on power-up to allow the internal clock generator to stabilize. the power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay after the oscillator becomes active. if the reset pin is low at the end of this 4064 cycle delay, the mcu will remain in the reset condition until reset goes high. 5.3 reset pin the mcu is reset when a logic zero is applied to the reset input for a period of one and one-half machine cycles (t cyc ). 5.4 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop time-out was generated. the cop reset function is a software programmable option. refer to 12.4 cop watchdog reset for more information on the cop.
general release specification motorola resets mc68hc(7)05cj4 5-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 5-1. power-on reset and reset t rl reset notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. osc1 2 i nternal clock 1 i nternal a ddress bus 1 i nternal data bus 1 new pch new pcl op code op code pch pcl 3 dummy 1fff new pc new pc 1ffe 1ffe 1ffe new pc new pc 1ffe 1fff 1ffe dummy v dd 4064 t cyc t vddr t cyc
general release specification mc68hc(7)05cj4 modes of operation motorola rev. 2.1 6-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 6 modes of operation 6.1 introduction the mc68hc05cj4 has the following operating modes: single-chip mode (scm) and self-check mode. in the mc68hc705cj4, the self-check mode becomes bootstrap mode. the single-chip mode allows maximum use of pins for on-chip peripheral functions. the self-check capability of mc68hc05cj4 provides an internal check to determine if the device is functional. the bootstrap loader mode is provided for eprom programming, dumping eprom contents, and reading programs into the internal ram and executing it. this is a very versatile mode because essentially on the special purpose program that is bootloaded into the internal ram has no limitations. this section also provides a description of the low-power modes. 6.2 mode entry the mode entry is done at the rising edge of the reset pin. once the device enters one of the four modes, the mode can be changed only by external reset not software. at the rising edge of the reset pin, the device latches the states of the irq, pb6 and pb7 pins and places itself in the specified mode. while the reset pin is low, all pins are configured as single-chip mode. table 6-1 shows the states of irq and pb6:7 pins for each mode. see figure 6-1. table 6-1. mode select summary mode reset irq pb6 pb7 single-chip mode l or h x x self-check/bootstrap mode v tst hx v tst = 1.8 x v dd h = v dd l = gnd
general release specification motorola modes of operation mc68hc(7)05cj4 6-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 6-1. mc68hc(7)05cj4 mode entry diagram 6.3 single-chip mode (scm) in this mode, all address and data bus activity occurs within the mcu so no external pins are required for these functions. the single-chip mode allows the maximum number of i/o pins for on-chip peripheral functions, port a through port d. 6.4 self-check/bootstrap mode in this mode, the reset vector is fetched from a 240-byte internal self-check (bootstrap for mc68hc705cj4) rom at $1f00:$1fef. the self-check rom contains a self-check program to test the functions of internal modules. the bootstrap rom contains a small program which reads a program into the internal ram and then passes control to that program at location $0020, or executes eprom programming sequence and dumps eprom contents. since these modes are not normal user modes, all of the privileged control bits are accessible. this allows the self-check/bootstrap mode to be used for self testing the device. 6.5 low-power modes the following sub-sections describe the low-power modes. figure 6-2 provides a timing diagram of the stop recovery mode and figure 6-3 a flowchart for the stop and wait modes. reset irq1 pb6:7 single-chip v tst h l h l h l * v tst = 1.8 x v dd
general release specification mc68hc(7)05cj4 modes of operation motorola rev. 2.1 6-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 6.5.1 stop mode the stop instruction places the mcu in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. during the stop mode, the tcsr (timer 2) bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. the i bit in the ccr is cleared to enable external interrupts. all other registers and memory remain unaltered. all input/output lines remain unchanged. the processor can be brought out of the stop mode only by an external interrupt or reset. 6.5.2 stop recovery the processor can be brought out of the stop mode only by an external interrupt or reset. figure 6-2. stop recovery timing diagram 6.5.3 wait mode the wait instruction places the mcu in a low-power consumption mode, but the wait mode consumes more power than the stop mode. all cpu action is suspended, but the timers and the oscillator remain active. any interrupt or reset will cause the mcu to exit the wait mode. 1ffe 1ffe 1ffe 1ffe 1fff internal address bus internal clock irq 3 irq 2 reset osc1 1 reset or interrupt vector fetch notes: 1. represents the internal gating of the osc1 pin. 2. irq pin edge-sensitive software option. 3. irq pin level and edge-sensitive software option. t rl 4064 t cyc t ilch t lh
general release specification motorola modes of operation mc68hc(7)05cj4 6-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 during the wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the timers may be enabled to allow a periodic exit from the wait mode. figure 6-3. stop/wait mode flowcharts external y stop oscillator active timer clock active processor clocks stopped interrupt ( irq) external reset reset turn on oscillator wait for time delay to stabilize 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt restart processor clock wait stop oscillator and all clocks clear i bit interrupt timer 1 interrupt ( irq) 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine y y y y n n n n n y interrupt sci interrupt spi n y n interrupt iic interrupt timer 2 y y n n
general release specification mc68hc(7)05cj4 input/output ports motorola rev. 2.1 7-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 7 input/output ports 7.1 introduction in user mode there are 32 lines arranged as four 8-bit ports. most of these port pins are programmable as either inputs or outputs under software control of the data direction registers, though some are input only. note to avoid a glitch on the output pins, write data to the i/o port data register before writing a one to the corresponding data direction register. 7.2 port a port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $0000 and the data direction register (ddr) is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 7.3 port b port b is an 8-bit bidirectional port. the port b data register is at $0001 and the data direction register (ddr) is at $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port pin to output mode. 7.4 port c port c is an 8-bit bidirectional port. the port c data register is at $0002 and the data direction register (ddr) is at $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. pc7 has a high current sink and source capability.
general release specification motorola input/output ports mc68hc(7)05cj4 7-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 7.5 port d port d is an 8-bit fixed input port. four of its pins are shared with the spi subsystem, two are shared with the i 2 c subsystem and two more are shared with the sci subsystem. during reset, all eight bits become valid input ports because all special function output drivers associated with the sci, i 2 c and spi subsystems are disabled. 7.6 input/output programming port pins for ports a, b, and c may be programmed as inputs or outputs under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). ports a, b, and c have an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set to a logic one. a pin is configured as an input if its corresponding ddr bit is cleared to a logic zero. at power-on or reset, all ddrs are cleared, which configures all pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. for further information see table 7-1 and figure 7-1. table 7-1. i/o pin functions r/ w ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read.
general release specification mc68hc(7)05cj4 input/output ports motorola rev. 2.1 7-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 7-1. i/o circuitry data direction register bit latched output data bit i/o input reg bit input i/o output internal hc05 connections pin
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 8 serial communications interface 8.1 introduction this is an nrz asynchronous communication system with internal baud rate generation circuitry. it can be configured for eight or nine data bits. the baud rate generator is programmable to allow flexibility in choosing baud rates. there is a receiver wake-up feature, an idle line detect feature and various error detection features. two port d pins provide the external interface for the transmitted data (txd) and the received data (rxd). 8.2 transmit operation this transmitter includes a transmit serial shift register and a parallel transmit data register (forming a double buffered system). the transmit serial shift register is internal to the transmit logic and may not be read or written directly by the cpu. the output of this serial shifter is connected to the txd pin (port d bit 1) as long as the transmitter is enabled (te control bit set or te clear but a transmit operation being completed). if the transmitter is enabled (te = 1), tc will be set at the end of a frame provided the transmit data register is empty (tdre = 1), there is no pending preamble, and no pending break. the transmitter can operate in either of two formats as specified by the m control bit in the sccr1 register. when m is zero, one start bit, eight data bits, and one stop bit is the selected mode. when m is one, one start bit, nine data bits, and one stop bit is the selected mode. the most common standard word format for nrz serial communication is one start bit (logic zero or space) followed by eight data bits (lsb first) and one stop bit (logic one or mark). if the nine data bit mode is selected, software control (and overhead) of the ninth bit may be used to support a number of special formats. the ninth data bit is positioned as two bits in the sccr1 register (r8 and t8). it remains unchanged after transmission and may be used again without having to re-write it. some examples of its use include: ? start, eight data, two stop bits ? start, eight data, parity, one stop w/ odd, even, mark, or space parity
general release specification motorola serial communications interface mc68hc(7)05cj4 8-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ? start, seven data, parity, two stop bits w/ odd, even, mark, or space parity ? start, eight data, address/control, one stop bit where address/control bit identifies special command words when the transmit logic is enabled by writing a one to the te control bit in the sccr2 register, a check is made to determine whether or not the transmit serial shift register is empty. if it was empty (indicated by tc = 1) a preamble word of all ones and no start bit is transmitted and normal data transmission begins. if the shifter was not empty (tc = 0) then normal shifting continues until the current word is shifted out including the stop bit and then a preamble is transmitted and normal data transmission continues. data to be transmitted originates from the cpu and enters the serial transmit logic when it is written to the data register (scdr). if 9-bit data is to be transmitted, the t8 bit should be initialized before writing to the scdr. writes to the scdr register access the write-only tdr and reads access the read-only rdr. before writing to the tdr, the program should read the scsr status register. if the tdre bit in scsr is clear, useful data is in the tdr and writes to tdr would erroneously overwrite this information. if the tdre bit is set it indicates that the tdr is empty and a subsequent write to tdr will fill the tdr and automatically clear tdre. as soon as the data in the serial shifter has finished shifting out a check is made to see if there is a new byte of data in the tdr. if tdre = 0, then data is transferred from the tdr to the transmit shifter and tdre becomes set automatically (optionally causing an interrupt). this transfer from tdr to the shifter is synchronized with the baud rate clock. if tdre = 1 when the shifter becomes available and there is no preamble pending, then an idle condition will be entered in which the txd pin will remain high. messages may be separated by a serial preamble of 10 (11 if nine data bit format is specified) bit times of marks (ones). to force this separation preamble with minimum idle line time the following sequence is used: 1. write last byte of first message to tdr. 2. wait for tdre to go high, indicating the last byte has been transferred to the shifter. 3. clear transmit enable (te) and then set te back to one. this queues a preamble to immediately follow the transmission of the last character of the first message (including stop bit). 4. write first byte of second message to tdr. in this sequence, if the first byte of the second message is not transferred to the tdr prior to the finish of the preamble transmission, then the transmit data line will simply mark idle until the tdr is finally written. also, if the last byte of the first message finishes shifting out (including stop bit) and te is clear then the tc bit will
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 go high and transmission will be considered to be complete. the txd pin also will revert to being a general purpose input line. when the te control bit is cleared (and left clear), the transmit logic gives up control of the port d pin in the following controlled manner. if no data is being shifted out and the transmitter is in an idle state (tc = 1), then when te is cleared the port d pin immediately reverts to being a general purpose input line. if a transmission was still in progress (tc = 0), the character in the transmit shift register will continue to be shifted out normally including any stop bit. when this character is finished, the txd pin reverts to being a general purpose input line regardless of whether any data is pending in the tdr (tdre is a dont care). in order to avoid accidentally cutting off the transmitter before the last character in a message, the software should always wait for tdre to go high following the last write to tdr before clearing te. another transmit-related sci function is the send break function. this function is used to abort transmissions by sending a minimum of 10 (11 if nine data bit format is specified) bit times of space (logic zeros). the break function is invoked by writing a one to the sbk bit in the sccr2 register. if sbk is set while a transmission is in progress, then the character in the transmit shift register will be finished normally (including stop bit) before the break function begins. the logic zero state on the txd line will be a minimum of 10 (11) bit times but will continue indefinitely as long as the sbk bit remains set. to guarantee the minimum break time, sbk should just be toggled quickly to a one and back to zero. after a break period, at least one bit time of mark (logic one) will be transmitted to guarantee recognition of a subsequent start bit. 8.3 receive operation the receive logic in the sci is divided into two major sections. the first section is a front end that synchronizes to the asynchronous receive data and evaluates the logic sense of each bit in the serial stream. the second section controls the functional operation and the interface to the cpu. 8.3.1 receiver front end due to the asynchronous nature of this serial communication system, the receiver has a significant section of logic dedicated to gaining bit time synchronization with the incoming data and evaluating the logic sense of each bit time in the serial data stream. an understanding of this receiver front end logic is required before the functional operation of the remaining receive logic can be explained. this receiver front end logic uses a clock that is 16 times the baud rate frequency as a sampling clock (the sampling clock is called the rt clock in the following discussions.). in the remainder of this discussion, one rt is understood to be 1/16 of a bit time.
general release specification motorola serial communications interface mc68hc(7)05cj4 8-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a few definitions will help in understanding the following discussions. bit time a bit time is the period of time required to serially transmit or receive one bit of data and is equal to one cycle of the baud rate frequency. mark/space standard nrz format is sometimes called mark/space format where a mark is a bit time of logic one and a space is a bit time of logic zero. start bit a start bit is a bit time of logic zero which indicates the beginning of a data frame. a start bit must begin with a one to zero transition and is preceded by at least one bit time of logic one. stop bit a stop bit is one bit time of logic one which indicates the end of a data frame. frame a frame consists of a start bit followed by a specified number of data or information bits terminated by a stop bit. the number of data or information bits depends on the format specified and must agree between the transmitting device and the receiving device. the most common frame format is one start bit followed by eight data bits (lsb first) terminated by one stop bit for a total of ten bit times in the frame. this device is also capable of operating in a nine data bit format as described elsewhere in this specification. when the receiver is first enabled, by writing a one to the re bit in the sccr2 register, the receiver front end logic begins an asynchronous search for a start bit. the goal of this search is to gain synchronization with a frame. this bit time synchronization is done at the beginning of each frame so that small differences in the baud rate of the receiver and transmitter are not cumulative. the circuit also resynchronizes on all one-to-zero transitions in the serial data stream. the sequence of events in searching for a start bit is as follows: 1. sample rxd input during each rt period and maintain these samples in a serial pipeline. * if rxd is already low, do not begin the start bit search - go to step 1. * if rxd is high, look for two more high rt samples before beginning the start bit search. stay in step 1 until a total of three consecutive high rt samples have been received. 2. rxd was low during this rt period and high during the previous three periods. consider this sample to be time rt1 and the official start of the start bit search.
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3. ignore the sample at rt2 and sample rxd at rt3. call this the first test sample. 4. ignore the sample at rt4 and sample rxd at rt5. call this the second test sample. if test samples at rt3 and rt5 were both high, assume that the low detected at rt1 was noise and go back to step 1 else continue. 5. ignore the sample at rt6 and sample rxd at rt7. call this the third test sample. if any two of the test samples at rt3, rt5, or rt7 were high assume that the low detected at rt1 was noise and go back to step 1 else continue. 6. a valid start bit has been found and synchronization has been achieved. from this point on until the end of the frame the rt clock will increment to rt16 and start over at rt1 where rt1 is considered to be the beginning of a bit time and rt16 is considered to be the end of a bit time. note any one-to-zero transition will re-synchronize the rt clock and may shift the assumed location of rt1. upon detection of a valid start bit, synchronization has been established and locked to the internal 16 times baud rate clock. the incoming data is no longer considered asynchronous until after reception of the stop bit, at which time a new asynchronous search for a start bit is initiated. during each bit time of the frame, including the start and stop bit times, three logic sense samples are taken at rt8, rt9, and rt10. the logic sense of the bit time is taken to be the sense of the majority of these three samples (except the start bit, which is assumed to be logic sense zero regardless of the rt8 C rt10 samples). note that during the start bit time, samples were also taken at rt1, rt3, rt5, and rt7 and the samples taken at rt8, rt9, and rt10 during the start bit time are only used for possible setting of a working noise flag. there is a working noise flag associated with each received frame which implies whether or not the information in the frame is likely to be in error. if the noise flag is clear, it implies good information, and, if this flag is set, it implies that the data may (but probably does not) contain errors. at the beginning of a frame, the working noise flag starts out at zero. if any of the samples taken at rt3, rt5, or rt7 during the start bit search was a high, the working noise flag will be set. also, if the samples taken at rt8, rt9, and rt10 during any one bit time (including the start bit, all data bits, optional ninth bit, and stop bit) do not all three agree, the working noise flag will be set.
general release specification motorola serial communications interface mc68hc(7)05cj4 8-6 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 the following figures demonstrate the operation of the start bit search and synchronization procedure. the logic sense sampling at rt8, rt9, and rt10 assumes that the probability of noise affecting three consecutive rt samples is acceptably low, so the examples will not consider any such cases. example 1 shows the ideal case with no noise present. figure 8-1. start search example 1 example 2 shows the start bit search and resynchronization process being restarted because the first low detected was determined to e noise rather than being the beginning of a start bit time. since the noise was before the start bit was found, it would not cause the working noise flag to be set. figure 8-2. start search example 2 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 *rt1 rt2 rt3 11111 111 1000000 0 perceived start bit actual start bit lsb * = restart rt clock *rt1 *rt1 *rt1 *rt1 *rt2 *rt3 *rt4 *rt5 *rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 *rt1 rt2 rt3 1110 111 1000000 0 perceived start bit actual start bit lsb * = restart rt clock
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 in example 3, noise is perceived as the beginning of a start bit although the test sample at rt3 was high setting the working noise flag. even though this shows improper alignment of perceived bit time boundaries to actual bit time boundaries the logic sense samples taken at rt8, rt9, and rt10 will fall well within the correct actual bit time and data recovery should still be good. figure 8-3. start search example 3 in example 4, a large burst of noise is perceived as the beginning of a start bit, although the test sample at rt5 was high, setting the working noise flag. even though this shows a worst case alignment of perceived bit time boundaries to actual bit time boundaries, the logic sense samples taken at rt8, rt9, and rt10 will fall within the correct actual bit time, and data recovery should still be successful. figure 8-4. start search example 4 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 *rt1 rt2 rt3 rt4 rt5 rt6 rt7 11111 1 00000 0 actual start bit lsb * = restart rt clock : perceived start bit actual start bit perceived start bit *rt1 *rt1 *rt1 *rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 *rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 1110 1 0000 0 lsb * = restart rt clock :
general release specification motorola serial communications interface mc68hc(7)05cj4 8-8 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 example 5 shows the effect of noise early within the start bit time. although this noise does not affect proper synchronization with the start bit time, it does set the working noise flag. figure 8-5. start search example 5 in example 6, a large burst of noise near the beginning of the start bit caused the start bit search to be restarted. during the rt period after the restart at rt7, a low was sensed but the preceding three rt samples were not all high so no falling edge could be recognized. since the circuit cannot locate the start bit, the frame will be received as a framing error, improperly received, or missed entirely depending on the data in the frame and when the start bit search logic synchronized on what it thought was a start bit. in the narrative prior to the examples, it was stated that any burst of noise that could cause three consecutive rt samples to sense the incorrect data level was so improbable that it would not be considered. example 6 shows two separate short duration noise incidents which are so specifically positioned within the frame that this case could be ignored on similar grounds of very low probability. figure 8-6. start search example 6 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 *rt1 rt2 rt3 11111 111 1010000 0 perceived start bit actual start bit lsb * = restart rt clock *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 11111 111 10 1 0 000 0 actual start bit lsb * = restart rt clock 100 000 0ddd see explanation no start bit found
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 in example 7, the majority of the logic sense samples taken at rt8, rt9, and rt10 during the start bit time were high, suggesting that the logic sense should be one but recall that, for the start bit time only, the logic sense indicated by the rt8, rt9, and rt10 samples is overridden to zero. figure 8-7. start search example 7 to understand why start bit times do not obey the majority sampling of rt8, rt9, and rt10, consider what would happen if the start bit noise shown in example 7 occurred at a time when the sum of logic sense one bit times at the end of the preceding frame and the number of logic sense one bit times at the beginning of this frame was greater than the number of bits in a frame. the wake-up logic would erroneously wake up a receiver that did not force the start bit to be seen as a zero. also, consider that in order for the start bit to have been recognized, at least three of the samples taken at rt1, rt3, rt5, and rt7 had to be lows. even if two of the samples taken at rt8, rt9, and rt10 were high, then there would still be a majority of all samples taken during the start bit time in favor of a logic zero decision. *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 *rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 *rt1 rt2 rt3 11111 111 1000011 0 perceived start bit actual start bit lsb * = restart rt clock
general release specification motorola serial communications interface mc68hc(7)05cj4 8-10 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8.3.2 receiver functional operation this receiver includes a receive serial shift register and a parallel receive data register (this is called a double buffered system because after a complete character is shifted in serially it is immediately moved to a parallel register so that the subsequent character can be shifted in without requiring the cpu to immediately service the first character.). the receive serial shift register is internal to the receive logic and may not be read or written directly by the cpu. the input of this serial shifter is connected to the majority sampling logic of the front end. the receiver can operate in either of two formats as specified by the m control bit in the sccr1 register. the most common standard word format for nrz serial communication is one start bit (logic zero or space) followed by eight data bits (lsb first) followed by one stop bit (logic one or mark). in addition to this standard format this circuit provides hardware for a nine data bit format as follows: one start bit, eight data bits (lsb first), ninth data bit, and one stop bit. if the nine data bit mode is selected, software control (and overhead) of the ninth bit may be used to support a number of special formats. the ninth data bit is positioned as r8 in the sccr1 register. some examples of its use include: ? start, eight data, two stop bits ? start, eight data, parity, one stop w/ odd, even, mark, or space parity ? start, seven data, parity, two stop bits w/ odd, even, mark, or space parity ? start, eight data, address/control, one stop bit where address/control bit identifies special command words the receive logic is enabled when the receive enable (re) bit in the sccr2 register is set to one. when re is zero the receive logic is initialized and most of the receiver front end logic is disabled. the receiver front end logic drives a state machine (running off the rt clock) and provides the derived logic level for each bit time. this state machine controls when the front end logic is to sample the rxd pin and controls when data is to be passed to the receive serial shift register. data is shifted into the receive serial shift register according to the most recent synchronization of the rt clock. from this point on in the discussion, data reception may be considered to be synchronous. the logic sense of each bit in the frame is determined from the majority of three samples taken near the middle of the bit time except the start bit which is forced to be shifted in as a zero regardless of the result of the majority sampling logic (see the discussion of the receiver front end logic). the next eight bits shifted in are the basic data byte (lsb is shifted in first). the next bit shifted in depends on the mode selected by the m bit in sccr2. if the nine data bit format is selected, the next bit received after the msb is the ninth data bit. it will be transferred to its appropriate
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 position in r8 at the same time the lower 8 bits of data are transferred from the receive serial shift register to scdr. the last bit to be shifted in for each frame is the stop bit, which should be a logic one. if a logic zero bit time is sensed where a stop bit was expected, it is called a framing error. the framing error is usually caused by mismatched baud rates between the transmitter and receiver, or by noise that caused the start bit to be missed so that the frame was synchronized incorrectly. it should be noted that it is possible for a framing error to go undetected because there is a chance that the data sampled where the stop bit was expected could have been a logic one anyway. when the stop bit is received, the frame is considered to be complete and the received character in the receive serial shift register is normally transferred in parallel to the receive data register (rdr). several other actions occur at the same time this transfer is taking place. the abnormal case where the rdrf flag in the scsr register is set at the time the transfer was to occur is called an overrun because a new data character was received from the serial line before a previously received character was serviced by the cpu. no transfer to rdr is allowed while rdrf or or is set. parallel transfers and associated actions to status bits occur at a time that will not interfere with cpu access to the affected registers. all status flags associated with a serially received frame are simultaneously set. when a complete frame has been serially received either the receive data register full (rdrf) or the over run (or) status flag always will be set. when the receive interrupt enable (rie) control bit in the sccr2 register is set to one, a hardware interrupt request will result if either rdrf or or is set indicating reception of a new frame of data. the receive status bits noise flag (nf) and framing error (fe) do not separately cause hardware interrupts because they are never set without being accompanied by rdrf. the nf and fe flags are always associated with the data in the rdr so they never get set with or but do get set with rdrf if the associated frame had the corresponding error(s). an automatic clearing mechanism is associated with the receiver status bits. the mechanism involves reading the scsr register followed by reading the rdr register (scdr read). when the rdr is read, any of the receive status bits (rdrf, idle, or, nf, or fe) that were set when the scsr register was read will automatically be cleared.
general release specification motorola serial communications interface mc68hc(7)05cj4 8-12 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8.3.3 idle line detect the receive logic hardware includes the ability to detect an idle line. this can be useful in a system to indicate when one message was finished and another was about to be started. an idle line is defined as a minimum of 10 (11 if nine data bit format is selected) bit times of continuous logic ones on the rxd line. during a normal message, there is no idle time between frames, so even if all information bits in a frame were logic ones the start bits would ensure that at least one logic zero bit time occurred for each frame and idle would not get set. when the rxd line goes idle for the minimum required time, the idle status bit in scsr gets set. if the idle line interrupt enable (ilie) bit in the sccr1 register is set then a hardware interrupt sequence also will be requested when idle gets set. the idle status bit is cleared by reading the scsr register (with idle set) followed by reading the rdr register. idle will not be set again until after at least one character is received. this prevents an rxd line that remains idle for a long period of time from causing several interrupts. 8.3.4 receiver wakeup the receiver logic hardware also supports a receiver wake-up function intended for systems having more than one receiver. with this function, the transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. receivers not addressed invoke the receiver wake up function which puts these receivers in a dormant state for the remainder of the unwanted message. this eliminates any further software overhead to service the remaining characters of the unwanted message and thus improves performance. the receiver is placed in wake-up mode by writing a one to the receiver wake-up (rwu) bit in the sccr2 register. while rwu is set, all of the receive status flags (rdrf, idle, or, nf, and fe) are inhibited (cannot be set). note that specification of receiver wake-up mode inhibits the use of the idle line detect function. although rwu may be cleared by a write to sccr, it is normally left alone by software and gets cleared automatically by hardware with one of the two methods explained in the following paragraphs. the sci offers a choice of two methods for waking up receivers from the dormant state. the first method is called idle line wake up. the second method is called address mark wake up and operates by using the msb to differentiate between address information (msb set) and data information (msb clear). the wake control bit in the sccr1 control register is used to select which method of automatic hardware wake up is to be used. if the wake bit is clear, idle line wake up is specified and if wake is set to one, address mark wake up is selected.
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8.3.5 idle line wakeup to use this receiver wake up method in an actual system, a software device addressing scheme is established to allow the transmitting device(s) to direct messages to individual receivers or groups of receivers. this addressing scheme is purely a software device and may take any form as long as all transmitting or receiving devices are programmed to understand the same scheme. the addressing information is usually the first frame(s) in a message so that uninterested receivers are burdened with only these minimum addressing frames. all receivers are awake (rwu bit is clear) when each message begins and as soon as a receiver determines that the message is not intended for it, it sets its rwu bit which inhibits flag setting until the rxd line goes idle at the end of the message. as soon as an idle line is detected (in hardware) while the rwu bit is set, the receiver hardware will force the rwu bit to zero so that the first frame in the next message can be received. this method of receiver wake up requires that a minimum of one frame time of idle line be imposed between messages and that no idle time is allowed between frames within a message. 8.3.6 address mark wakeup in this method of receiver wake up, all serial frames consist of seven (or eight) information bits plus an msb which is used to indicate an address frame (when set to one mark). the first frame(s) of each message are addressing frames and all receivers in the system evaluate these marked address frames to determine whether or not the subsequent message is intended for a particular receiver. as soon as a receiver determines that a message is not intended for it, it invokes the receiver wake-up function (by setting rwu) so that no additional software overhead is required for the rest of the message. when the next message begins, its first frame will have the ninth bit set, which will automatically clear the rwu bit and enable normal frame reception. the first frame whose ninth bit is set (address marked) also will be the first frame to be received after wake up because rwu gets cleared before the stop bit for that frame is serially received. this method allows messages to include idle times, unlike the first wake-up method, but efficiency is lost due to the extra bit time (address bit) which is required in all frames.
general release specification motorola serial communications interface mc68hc(7)05cj4 8-14 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8.4 sci register descriptions the following subsections provide a description of the sci registers. 8.4.1 sci baud rate control register the value in this register determines the baud rate of the sci. scp1:0 set the prescaler and scr2:0 set the final divider chain.the desired baud rate is determined by: baud = bus clock divided by 16 divided by (scp1:scp0) divided by (scr2:scr0). read: anytime write: anytime scp1:scp0 sci prescaler these bits control the prescaler as shown in table 8-1. bit 7 654321 bit 0 $000d baud read: 00 scp1 scp0 0 scr2 scr1 scr0 write: reset: 00000uuu = unimplemented u = unaffected figure 8-8. sci baud rate control register table 8-1. scp1:scp0 select scp bit e*/16 divided by crystal frequency (f osc ) mhz 1 0 4.194304 4.0 2.4576 2.0 1.8432 0 0 1 131.072 khz 125.000 khz 76.80 khz 62.50 khz 57.60 khz 0 1 3 43.691 khz 41.666 khz 25.60 khz 20.833 khz 19.20 khz 1 0 4 32.768 khz 31.250 khz 19.20 khz 15.625 khz 14.40 khz 1 1 13 10.082 khz 9600 khz 5.907 khz 4800 khz 4430 hz * e is the internal bus clock (osc/2)
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 scr2:scr0 sci rate select these three bits can be used to divide further the output of the prescaler. see table 8-2. table 8-2. scr2:scr0 select scr bit prescaler divided by representative highest prescaler baud rate output 2 1 0 131.072 khz 32.768 khz 76.80 khz 19.20 khz 9600 hz 0 0 0 1 131.072 khz 32.768 khz 76.80 khz 19.20 khz 9600 hz 0 0 1 2 65.536 khz 16.384 khz 38.40 khz 9600 hz 4800 hz 0 1 0 4 32.768 khz 8.192 khz 19.20 khz 4800 hz 2400 hz 0 1 1 8 16.384 khz 4.096 khz 9600 hz 2400 hz 1200 hz 1 0 0 16 8.192 khz 2.048 khz 4800 hz 1200 hz 600 hz 1 0 1 32 4.096 khz 1.024 khz 2400 hz 600 hz 300 hz 1 1 0 64 2.048 khz 512 hz 1200 hz 300 hz 150 hz 1 1 1 128 1.024 khz 256 hz 600 hz 150 hz 75 hz
general release specification motorola serial communications interface mc68hc(7)05cj4 8-16 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8.4.2 sci control register 1 (sccr1) read: anytime write: anytime r8 receiver bit 8 this bit provides storage for the ninth bit in the receive data byte (if m = 1). t8 transmit bit 8 this bit provides storage for the ninth bit in the transmit data byte (if m = 1). m mode (select character format) read: anytime write: anytime 0 = 1 start, 8 data, 1 stop bit 1 = 1 start, 8 data, ninth data, 1 stop bit wake wake up by address mark/idle read: anytime write: anytime 0 = wake up by idle line recognition 1 = wake up by address mark (8th or 9th -last- data bit set) bit 7 654321 bit 0 $000e sccr1 read: r8 t8 0 m wake 000 write: reset: u u 0 u u 0 0 0 = unimplemented u = unaffected figure 8-9. sci control register 1
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8.4.3 sci control register 2 (sccr2) read: anytime write: anytime tie transmit interrupt enable when this control bit is set to a one, an sci interrupt will be requested whenever the tdre status flag is set. tcie transmit complete interrupt enable when this control bit is set to a one, an sci interrupt will be requested whenever the tc status flag is set. rie receiver interrupt enable when this control bit is set to a one, an sci interrupt will be requested whenever the rdrf status flag or the or status flag is set. ilie idle line interrupt enable when this control bit is set to a one, an sci interrupt will be requested whenever the idle status flag is set. te transmitter enable when this control bit is set, the sci transmit logic is enabled and the txd pin (port d bit 1) is dedicated to the transmitter. the te bit can be used to queue an idle preamble. re receiver enable this control bit (when set) enables the sci receive circuitry. rw receiver wake-up control when set this control bit enables the wake-up function and inhibits further receiver interrupts. normally, hardware wakes the receiver by automatically clearing this bit. bit 7 654321 bit 0 $000f sccr2 read: tie tcie rie ilie te re rwu sbk write: reset: 00000000 figure 8-10. sci control register 2
general release specification motorola serial communications interface mc68hc(7)05cj4 8-18 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sbk send break to generate a break code (at least 10 or 11 contiguous zeros), a one is written into this bit. as long as sbk remains set to a one, the transmitter will send zeros. if sbk is toggled on and off, the transmitter will send only 10 (or 11) zeros and then revert to mark idle or sending data. 8.4.4 sci status register (scsr) the bits in this register are set by various conditions in the sci hardware and are automatically cleared by special acknowledge sequences. the receive-related flag bits in scsr (rdrf, idle, or, nf, and fe) are all cleared by a read of the scsr register followed by a read of the transmit/receive data register. however, only those bits which were set when scsr was read will be cleared by the subsequent read of the transmit/receive data register. the transmit-related bits in scsr (tdre and tc) are cleared by a read of the scsr register followed by a write to the transmit/receive data register. read: anytime (used in auto clearing mechanism) write: has no meaning or effect tdre transmit data register empty flag this bit is set when the byte in the transmit data register is transferred to the serial shift register. new data will not be transmitted unless the scsr register is read before writing to the transmit data register. reset sets this bit. tc transmit complete flag this bit is set to indicate that the sci transmitter has no meaningful information to transmit (no data in shifter, no preamble, no break). when tc is set, the serial line will go idle (continuous mark). reset sets this bit. rdrf receive data register full flag this bit is set when the contents of the receiver serial shift register is transferred to the receiver data register. bit 7 654321 bit 0 $0010 scsr read: tdre tc rdrf idle or nf fe 0 write: reset: 11000000 = unimplemented figure 8-11. sci status register
general release specification mc68hc(7)05cj4 serial communications interface motorola rev. 2.1 8-19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 idle idle line detected flag this bit is set when a receiver idle line is detected (the receipt of a minimum of 10/11 consecutive ones). this bit will not be set by the idle line condition when the rwu bit is set. once cleared, idle will not be set again until after rdrf has been set (until after the line has been active and becomes idle again). or over-run error flag this bit is set when a new byte is ready to be transferred from the receiver shift register to the receiver data register and the receive data register is already full (rdrf bit is set). data transfer is inhibited until this bit is cleared. nf noise error flag this bit is set if there is noise on a valid start bit, any of the data bits, or on the stop bit. the nf bit is set during the same cycle as the rdrf bit but does not get set in the case of an over run (or). fe framing error flag this bit is set when the word boundaries in the bit stream are not synchronized with the receiver bit counter (generated by the reception of a logic zero bit where a stop bit was expected). the fe bit reflects the status of the byte in the receive data register and the transfer from the receive shifter to the receive data register is inhibited in the case of over run. the fe bit is set during the same cycle as the rdrf bit but does not get set in the case of an over run (or). the framing error flag inhibits further transfer of data into the rdr until it is cleared. pf parity error flag this bit is set when the received datas parity does not match its parity bit. this feature is active only when parity is enabled. the type of parity tested for is determined by the pt (parity type) bit in sccr1.
general release specification motorola serial communications interface mc68hc(7)05cj4 8-20 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8.4.5 sci data register (scdr) scd7:scd0 serial data bits 7 to 0 read: reads access the 8 bits of the read-only sci receive data register (rdr) write: writes access the 8 bits of the write-only sci transmit data register (tdr) reset: does not affect this address bit 7 654321 bit 0 $0011 scdr read: scd7 scd6 scd5 scd4 scd3 scd2 scd1 scd0 write: unaffected by reset figure 8-12. sci data register
general release specification mc68hc(7)05cj4 serial peripheral interface motorola rev. 2.1 9-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 9 serial peripheral interface 9.1 introduction the term serial peripheral refers to the fact that this interface requires separate wires (signals) for data and clock. in this format, data does not contain an explicit clock. the spi scheme may be used to interconnect microcomputers located at a short distance (usually within a single black box or on the same pc card). this may comprise a system of one microcomputer and several slaves or may be a system of microcomputers, each having the capability of either master or slave. a practical system may include: 1. miso master in slave out 2. mosi master out slave in 3. sck1 serial clock 4. ss(n) slave select(s) this device also includes a programmable direction of data to select either msb or lsb first format. 9.2 signal description the following subsections provide a description of the spi signals. 9.2.1 master in slave out (miso) in slave mode , miso is the signal which is used to present data from a slave device to the bus. the miso pin will be placed in the high-impedance state when ever a slave device is not selected (ss = 1) by the bus master. see figure 9-2 for more information. four possible timing relationships may be chosen by use of the control bits (cpol) and (cpha). the slave device and a master device must be programmed to be in similar timing modes for proper data transfer. in the master mode (control bit mstr = 1), the function of mosi and miso are inverted within the device. therefore, the miso pin becomes the data input pin for a device which is in the master mode. (also, the function of sck1 switches from being an input for system clock to one of outputting the system clock.)
general release specification motorola serial peripheral interface mc68hc(7)05cj4 9-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 9.2.2 serial data in (mosi) in slave mode, mosi is the signal used to receive data from some master device. figure 9-2 shows the serial clock and data timing relationship. it should be noted that when a master device transmits data to a second device via the mosi line, the slave device (if it has the capability) will respond by sending data into the miso pin of the master device. this implies full duplex transmission with both data out and data in synchronized to the same clock signal which is provided by the master. moreover, the same shift register is used for data out and data in. thus, the byte transmitted is replaced by the byte received, removing the need for separate status bits for xmit empty and rec full. a single status bit, spif, is used to signify i/o operation complete. in the master mode, as noted above, the functions of mosi and miso are inverted. the mosi pin becomes the data output pin when the device is in the master mode. when a transfer of data is not taking place with a slave device the master drives the mosi line high. the master always allows the data onto the mosi pin a half-cycle before the clock edge (sck1) needed for the slave to latch the data internally. 9.2.3 serial clock in/out (sck1) in slave mode, the serial clock is used to move data both in and out of the device through its mosi and miso pins. the master and slave devices are capable of exchanging a byte of information during a sequence of eight clock pulses if wired to do so. in the slave mode, the sck1 pin becomes an input being sent from the master device for the external clock. in this case sck1 is asynchronous to the slave devices phase 1-2 clocks and read/write control, therefore synchronization must take place prior to transmission and after reception. this must be done on the byte level. the type of clock and its relationship with the data is controlled by bits cpol and cpha. reference figure 9-2. the clock rate control bits spr1 and spr0 have no function while the part is in the slave mode. in master mode , the clock is generated within the master device by a circuit driven from the bus clock. the clock rate is selected by bits (spr1, spr0) in the control register. the sck1 pin on the master device becomes a fixed output providing the system clock to an enabled slave or slaves. the clock is used by the master to latch incoming slave data on the miso pin and shift out data to the slave device on the mosi pin. the master and slave must be operated in the same timing mode. the type of clock and its relationship with the data is controlled by bits cpol and cpha. reference figure 9-2.
general release specification mc68hc(7)05cj4 serial peripheral interface motorola rev. 2.1 9-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 9.2.4 slave select ( ss) in slave mode , the slave select ( ss input) is generated by the master (parallel port may be used) and used to enable one of several slaves to accept and/or return data or enable several slaves to accept data. to insure a data byte transfer, the ss signal must be low prior to occurrence of sck1 and must not become high until after the 8th (last) sck1 cycle. figure 9-2 shows the clock (sck1) and data relationship. depending on the state of the cpha control bit, the ss pin pulled low: (1) allows the first bit of data onto the miso system line for transfer and (2) prevents the slave from reading or writing the data register. a further description of the effect of the ( ss) pin and (cpha) control bit on the i/o data register is given in the description of the (wcol) status flag. the (wcol) flag warns the slave if it has had a conflict between a transmission and a write of the data register. a high level on ss forces miso to the high-impedance state. also, sck1 and mosi are ignored by the disabled slave. in master mode , slave select ( ss) input is monitored to assure that it stays false (high). if slave select becomes true, the device immediately exits the master mode and becomes a slave (mstr = 0). also, control bit (spe) is forced to a zero causing all spi system pins to be inputs. an interrupt flag (modf) is set warning the device that the above events have occurred. the significance of this is that a collision has occurred; that is, two devices have both become masters. this is normally the result of software error, although some systems may allow the default master to knock all other masters off the bus if an erroneous bus state is detected. this is, of course, a catastrophic event and it is the responsibility of the default master to completely clean up the system.
general release specification motorola serial peripheral interface mc68hc(7)05cj4 9-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 9.3 spi registers the following subsections describe the spi registers. 9.3.1 spi control register (spcr) read: anytime write: anytime spie spi interrupt enable when this bit is set to a one a hardware interrupt sequence is requested each time the spif or modf status flag is set. spi interrupts are inhibited if this bit is clear or if the i bit in the condition code register is one. spe spi system enable when the spe bit is set the port d bits 2, 3, 4, and 5 are dedicated to the spi function. dod direction of data this bit determines the direction of data flow in or out of the serial shift register. when set, data is transferred lsb first. when cleared (the default state), data is transferred msb first. note figure 9-2 assumes a value of zero for this bit. mstr master/slave mode select 0 = slave mode 1 = master mode bit 7 654321 bit 0 $000a spcr read: spie spe dod mstr cpol cpha spr1 spr0 write: reset: 0000 uuuu u = unaffected figure 9-1. spi control register
general release specification mc68hc(7)05cj4 serial peripheral interface motorola rev. 2.1 9-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 cpol clock polarity cpha clock phase these two bits are used to specify the clock format to be used in spi operations. refer to figure 9-2. spr1, spr0 spi clock (sck1) rate select bits these bits are used to specify the spi clock rate. table 9-1. spi clock rates spr1 spr0 e clock divided-by frequency at e = 2 mhz (baud rate) 0 0 2 1.0 mhz 0 1 4 500 khz 1 0 16 125 khz 1 1 32 62.5 khz
general release specification motorola serial peripheral interface mc68hc(7)05cj4 9-6 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 9-2. spi clock/data relationships msb cpol:cpha = 0:0 cpol:cpha = 0:1 cpol:cpha = 1:0 cpol:cpha = 1:1 lsb msb lsb begin begin lsb msb end begin transfer sck1 sample (i) change (o) sel ss transfer sck1 sample (i) change (o) sel ss transfer sck1 sck1 change (o) sel ss transfer sck1 sample (i) change (o) sel ss end begin begin begin end begin
general release specification mc68hc(7)05cj4 serial peripheral interface motorola rev. 2.1 9-7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 9.3.2 spi status register (spsr) read: anytime write: has no meaning or effect spif spi interrupt request spif is set after the eighth sck1 cycle in a data transfer and it is cleared by reading the spsr register (with spif set) followed by an access (read or write) to the spi data register. wcol write collision status flag this error status flag is used to indicate that a serial transfer was in progress when the mcu tried to write new data into the spdr data register. the mcu write is disabled to avoid writing over the data being transmitted. no interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. this flag is automatically cleared by a read of the spsr (with wcol set) followed by an access (read or write) to the spdr register. modf spi mode error interrupt status flag this bit is set automatically by spi hardware if the mstr control bit is set to one and the slave select input pin becomes zero. this condition is not permitted in normal operation. this flag is automatically cleared by a read of the spsr (with modf set) followed by a write to the spcr register. bit 7 654321 bit 0 $000d spsr read: spif wcol 0 modf 0000 write: reset: 00000000 = unimplemented figure 9-3. spi status register
general release specification motorola serial peripheral interface mc68hc(7)05cj4 9-8 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 9.3.3 spi data register (spdr) read: anytime (normally only after spif flag set) write: anytime (see wcol write collision flag) reset: does not affect this register this 8-bit register is both the input and output register for spi data. in the spi system the 8-bit data register in the master and the 8-bit data register in the slave are linked by the mosi and miso wires to form a distributed 16-bit register. when a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the sck1 clock from the master so the data is effectively exchanged between the master and the slave. note that some slave devices are very simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. when writing the spdr, the data is written directly into the shift register and always shifted out in the same direction. to affect a change in the direction of data transfer, the data is loaded into the shift register in reverse order. for this reason, the dod bit must be written before data is loaded into the shift register when reading the spdr, a read data buffer is actually accessed. this buffer contains the last data byte received by the spi, and is updated during the cycle that spif is set (reception complete). bit 7 654321 bit 0 $000d spsr read: spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 write: reset: unaffected by reset figure 9-4. spi control register
general release specification mc68hc(7)05cj4 slave-only m-bus motorola rev. 2.1 10-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 10 slave-only m-bus 10.1 introduction motorola bus (m-bus for short) is a two-wire bidirectional bus which provides a simple, efficient method of providing data exchange between devices. it is fully compatible to the i 2 c bus standard.this device will contain a reduced version of the m-bus supporting only the slave mode. slave address recognition is provided in hardware with the value of the address being initialized by the user. also included is automatic generation of the acknowledge for both address and data, general call address recognition, and automatic clock stretching. 10.2 operation of somb and ninth-bit detector the somb consists of an 8-bit synchronous shift register, a start/stop detect circuit, a ninth-bit detector, and acknowledge detector. the serial data line (sda) and serial clock line (scl) share external connections with two bits of port d. these bits are not enabled during serial operation. the operation of the somb is best described in phases as shown in the following sub-sections. 10.2.1 after reset ? after the mcu has completed the reset operation, the somb is in the following condition: ? sme = 0. the somb is disabled and the parallel i/o are enabled. by definition, smie and smf also = 0. ? data = ?. the contents of the data register is unknown. to enable the somb, set sme and smie. this will allow the cpu to be interrupted upon reception of the slave address and/or serial data. 10.2.2 first reception the first reception must be proceeded by the start condition. by definition, the first reception consists of the slave address (seven bits) and the r/w bit. when the start condition is detected, the scl input is enabled and the slave's address is transferred from the address register into the shift register. on the first clock pulse the external serial data (msb of the master address) is shifted into the shift register,
general release specification motorola slave-only m-bus mc68hc(7)05cj4 10-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 and the first bit of the slave's address (already in the shifter) is shifted out. these two address bits are compared and if a match occurs, a counter is incremented. if a match does not occur, the counter is not incremented. this continues for the duration of the seven bits of address. after the eighth clock pulse, the shift register stops shifting. the smf bit is set after the ninth clock pulse. 10.2.3 after the first reception when smf is set, an interrupt request is generated to the cpu based on the following conditions: ? a start condition was recently detected. ? the address match counter equals seven ? smie is set if the address match counter is less than seven, this means that the slave is not being addressed. in that case, the start condition and smf are cleared and the scl input is disabled. the somb will ignore all further clock pulses until a subsequent start condition is detected. if a start condition was not detected on this transmission, then the address match counter is ignored and the data is treated as data. if the address is matched and the start was detected, the acknowledge is accomplished by forcing the sda line low (in hardware) and enabling the ninth-bit detector on the clock line. when the ninth clock pulse is detected on the clock line, the sda line is released automatically and the scl line is forced low to stretch the clock. when the serial service routine is completed , the user must release the clock line by writing a '0' to clkr. this serves as a mechanism for releasing the clock. note the m-bus address/data register (mbadr) now has the received data and bit zero contains the r/w bit from the master. this should be checked in software and the t/r bit in the slave should be set accordingly. the somb is now enabled and prepared to receive further data. it will stay in this mode until another start condition is detected, at which time this process will begin again.
general release specification mc68hc(7)05cj4 slave-only m-bus motorola rev. 2.1 10-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10.2.4 subsequent receptions after the first reception, the smf bit should be cleared by reading the status register followed by reading or writing the data register, this action clears the serial interrupt and enables the circuit to receive additional data. receiving and acknowledging the data is accomplished in the same way as the first reception. stretching the clock is done automatically after every transmission and must be released by the user each time. if the t/r bit is set, data is transmitted, if it is cleared data is received. the data register should be serviced before releasing the clock line in order to avoid data collision. 10.2.5 acknowledgment after address detection and data reception, an acknowledge is returned to the master during the ninth clock pulse. by setting the noack bit in the slave m-bus control register, the acknowledge function will be disabled for the following transmissions. during master read, an acknowledge is sent from the receiving master. the status of the acknowledge could be read from the mack bit in the slave m-bus status register during the service routine. this bit is used for detecting the master's acknowledge and end of transmission. by definition, the end of transmission is signaled from the master by the absence of the master acknowledge. in this case, the slave must clear the t/r bit to release the sda line. if the slave device does not release the sda line, the master may not be able to generate the stop condition. 10.2.6 stop condition the system is capable of detecting the stop condition. this is defined as the rising edge of the data line while the clock line is high. when this condition is detected, the system is brought to the state before the start condition. 10.2.7 general call address detect during address detect cycle (receiving cycle after the start detect), if the resulting address is $00, a condition of address match is generated. the user must determine whether this address match is a slave address match or a general call address match by reading the mbadr (slave mbus address/data register).
general release specification motorola slave-only m-bus mc68hc(7)05cj4 10-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10.3 slave m-bus control register (mbcr) smie slave m-bus interrupt enable when set, this bit enables the somb interrupt. there is only one source of interrupt which is from the smf bit. if smie is set when smf is set, an interrupt request is generated to the cpu. this bit is readable and writable and is cleared by reset. sme slave m-bus enable when set, this bit enables the somb. when clear, the circuit is disabled and all other status and control bits are cleared. if sme is cleared during a transmission, the transmission is aborted and all circuits are reset. this bit is readable and writable and is cleared by reset. t/r transmit/receive when set, the somb is configured to transmit data. upon reception of the scl from the master, the data in the shift register is transmitted out msb first. after the eighth clock pulse is received the ninth-bit detector is enabled. the sda line is not driven low in this case, but following the ninth clock bit the scl line is and smf is set (an interrupt is generated if smie is set). the purpose of stretching the clock is to allow the device to complete its service routine. the user must release the scl line to allow additional transmissions. this bit is readable and writable and is cleared by reset. noack no acknowledge this bit, when set, will disable the acknowledge for the following transmissions. this bit is used in multiple byte data transmission to terminate further transmissions when invalid data was sent from the master. the master, with no acknowledge being sent, will abort the transmission. this bit is readable and writable, and is cleared by reset. bit 7 654321 bit 0 $001d mbcr read: smie sme t/r noack 0000/1 write: clkr reset: 00000000/1 = unimplemented figure 10-1. m-bus control register
general release specification mc68hc(7)05cj4 slave-only m-bus motorola rev. 2.1 10-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clkr clock release this bit is used to release the scl line after a complete transmission. this bit can never be set, and writing a logic zero to it releases the clock line to allow further communications. note this bit reads a logic zero on the mc68hc705cj4 and a logic one on the mc68hc05cj4. special care must be taken on the mc68hc705cj4 as bit read-modify-write instructions may release the clock line. the other bits in this register (1-3) are not implemented and always read as zero.
general release specification motorola slave-only m-bus mc68hc(7)05cj4 10-6 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10.4 slave m-bus status register (mbsr) smf slave m-bus flag this bit is set after the ninth clock of a valid transmission. a valid transmission can be either a reception of a valid address following a start condition or transmission/reception of data after the a valid address is recognized. if smie is also set, an interrupt will be generated. this bit is cleared by first reading the mbsr with smf set, followed by reading or writing the m-bus address/data register. smf is also cleared when sme is cleared or by reset. stdf start detect flag this bit is set when a start condition is detected. it is provided as a means for the user to distinguish between an address and a data transmission. no interrupt is associated with this bit. clearing stdf is done by first reading the mbsr with stdf set, followed by reading or writing the m-bus address/data register. stdf is also cleared when sme is cleared or by reset. mack master acknowledge this bit shows the status to the acknowledge during the master read (slave write) operation. a master acknowledge happens during the ninth-bit of a slave transmission, when the slave releases the sda line and the master holds it low. when an acknowledge is sent by the master, mack will be set (logic one): if the master does not return any acknowledge, mack will be cleared. this provides a mean to detect if a master is signalling an end of transmission to the slave. no interrupt is associated with this bit. clearing mack is done by first reading the mbsr with mack set, followed by reading or writing the m-bus data register. mack is also cleared when sme is cleared or by reset note the other bits in this register (0C4) are not implemented and always read as zero. bit 7 654321 bit 0 $001e mbsr read: smf stdf mack 00000 write: reset: 00000000 = unimplemented figure 10-2. m-bus status register
general release specification mc68hc(7)05cj4 slave-only m-bus motorola rev. 2.1 10-7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10.5 m-bus address/data register (mbadr) first access: figure 10-3. m-bus address/data register subsequent accesses: figure 10-4. m-bus data address/register this register has a dual purpose. the initial write to the mbadr must be the slave address. this data is actually stored in a buffer for use after a start condition has been detected. subsequent writes go directly into serial shift register for transmission. the data register is not buffered. this means that reading or writing the mbadr during a transmission can corrupt the data. reads of the mbadr always give back the contents of the shift register, which is undefined until after the first reception. the address match is done for bits 1:7. bit 0 is not compared and contains the r/w bit when read. reset has no effect on the data register, but the address buffer is cleared to $00 and must be initialized by the user. bit 7 654321 bit 0 $001c mbadr read: msr7 msr6 msr5 msr4 msr3 msr2 msr1 msr0 write: mba7 mba6 mba5 mba4 mba3 mba2 mba1 mbr/w reset: uuuuuuuu u = unaffected bit 7 654321 bit 0 $001c mbadr read: msr7 msr6 msr5 msr4 msr3 msr2 msr1 msr0 write: mbd7 mbd6 mbd5 mbd4 mbd3 mbd2 mbd1 mbd0 reset: uuuuuuuu u = unaffected
general release specification motorola slave-only m-bus mc68hc(7)05cj4 10-8 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10.6 hardware flowchart of the somb figure 10-5. somb flowchart (sheet 1 of 2) b smf? start detect? stop detect? a y y a n n n ninth start detect stop detect a a clock? y y y n n n noack? acknowledge clock interrupt n y release stop detect? y a n c clock c d y y receive data bit release clock t/r = 1? n start start detect? stop detect? enable clock load address address smf? ninth address noack? acknowledge clock interrupt circuit and compare (per bit) start detect? stop detect? start detect stop detect b a a a a clock? match? y n y y y y y a y y y n n n n n n n n n y clkr=0 clkr=0 * noack bit should be set during the cycle before the current address/data transfer cycle. stretch stretch
general release specification mc68hc(7)05cj4 slave-only m-bus motorola rev. 2.1 10-9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 10-4. somb flowchart (sheet 2 of 2) note shaded area indicates an action of software. d c transmit data bit spif? start detect? stop detect? a y y a n n n y ninth clock? y n start detect a y n stop detect y n a update mack interrupt release data bus release clock stop detect? y n a c release clock clkr=0 clkr=0 clock stretch
general release specification motorola slave-only m-bus mc68hc(7)05cj4 10-10 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10.7 somb timing diagrams refer to figure 10-6, figure 10-7, and figure 10-8 for somb timing. figure 10-6. first reception timing figure 10-7. additional receptions timing scl driven low (hw slave) scl released (sw slave) sda driven low (hw slave) add msb add lsb r/w bit smf set scl sda start condition (master) slave address loaded (slave) ninth bit detected sda released (hw slave) scl driven low (hw slave) sda driven low (hw slave) stop condition (master) ninth bit detected data msb data lsb scl sda smf set scl released (sw slave) sda held low by master sda released (sw slave)
general release specification mc68hc(7)05cj4 slave-only m-bus motorola rev. 2.1 10-11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 10-8. transmissions (master read) timing ninth bit detected data msb data lsb scl sda scl released (sw slave) scl driven low (hw slave) smf set sda becomes output (slave) set mack bit from sda line (condition from master) sda released (hw slave)
general release specification mc68hc(7)05cj4 timer 1 motorola rev. 2.1 11-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 11 timer 1 11.1 introduction this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output compare interrupt. pulse widths can vary from several microseconds to many seconds. refer to figure 11-1. because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. note the i bit in the ccr should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur.
general release specification motorola timer 1 mc68hc(7)05cj4 11-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 11-1. timer 1 block diagram 11.2 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at anytime without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18:$19 (counter register) or $1a:$1b (counter alternate register). a read from only the least significant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register first addresses the most significant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the tcap edge select/ 16-bit comparator ocrh ocrl 16-bit counter tcmp ? 4 detect logic pin control logic trh trl icrh icrl icie toie ocie iedg olvl icf ocf tof timer overflow internal clock (xtal ? 2) internal data bus timer interrupt request atrl atrh
general release specification mc68hc(7)05cj4 timer 1 motorola rev. 2.1 11-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb must also be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at anytime without the possibility of missing timer overflow interrupts due to clearing of the tof. the free-running counter is configured to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt can also be enabled when counter rollover occurs by setting its interrupt enable bit (toie). 11.3 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the corresponding output compare flag (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare flag (ocf) is set or clear.
general release specification motorola timer 1 mc68hc(7)05cj4 11-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 11-2. timer 1 output compare operation because neither the output compare flag (ocf bit) or output compare register is affected by reset, care must be exercised initializing the output compare function with software. the following procedure is recommended: write to the high byte of the output compare register to inhibit further compares until the low byte is written. read the timer status register to clear the ocf bit if it is already set. write to the low byte of the output compare register to enable the output compare function. the purpose of this procedure is to prevent the ocf bit from being set between the writes to the high and low halves of the 16-bit output compare register. a software example follows: b7 16 sta ocrh inhibit output compare b6 13 lda t1sr clear ocf bit if set bf 17 stx ocrl ready for next compare 11.4 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (icf) is ocie int ocf 16-bit comparator counter high byte counter low byte 15 8 7 0 15 8 7 0 16-bit output compare 1 register pin control logic tcmp pin olvl =?
general release specification mc68hc(7)05cj4 timer 1 motorola rev. 2.1 11-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register ($14) msb, the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. figure 11-3. timer 1 input capture operation tcap pin counter low byte counter high byte 15 8 70 15 8 70 16-bit input capture register int latch edge select and detect icf icie iedg
general release specification motorola timer 1 mc68hc(7)05cj4 11-6 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 11.5 timer 1 control register (t1cr) the tcr is a read/write register containing five control bits. three bits enable interrupts associated with the timer status register flags icf, ocf, and tof. icie input capture interrupt enable 1 = interrupt enabled 0 = interrupt disabled oce output compare interrupt enable 1 = interrupt enabled 0 = interrupt disabled toie timer overflow interrupt enable 1 = interrupt enabled 0 = interrupt disabled bits 2:4 not used always read zero iedg input edge value of input edge determines which level transition on tcap pin will trigger free-running counter transfer to the input capture register reset does not affect the iedg bit. 1 = positive edge 0 = negative edge olvl output level value of output level is clocked into output level register by the next successful output compare and will appear on the tcmp pin 1 = high output 0 = low output bit 7 654321 bit 0 $0012 t1cr read: icie ocie toie 000 iedg olvl write: reset: 000000uu = unimplemented u = unaffected figure 11-4. timer 1 control register
general release specification mc68hc(7)05cj4 timer 1 motorola rev. 2.1 11-7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 11.6 timer 1 status register (t1sr) the t1sr is a read-only register containing three status flag bits. icf input capture flag 1 = flag set when selected polarity edge is sensed by input capture edge detector 0 = flag cleared when t1sr and input capture low register ($15) are accessed ocf output compare flag 1 = flag set when output compare register contents match the free-running counter contents 0 = flag cleared when t1sr and output compare low register ($17) are accessed tof timer overflow flag 1 = flag set when free-running counter transition from $ffff to $0000 occurs 0 = flag cleared when t1sr and counter low register ($19) are accessed bits 0:4 not used and always read as zero note status of icf, ocf, and tof flag bits are undefined after reset. accessing the timer 1 status register satisfies the first condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. bit 7 654321 bit 0 $0013 t1sr read: icfocftof00000 write: reset: x x x 00000 = unimplemented x = unde?ned figure 11-5. timer 1 status register
general release specification motorola timer 1 mc68hc(7)05cj4 11-8 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set, and 2. the lsb of the free-running counter is read but not for the purpose of servicing the flag. the counter alternate register at address $1a and $1b contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at anytime without affecting the timer overflow flag in the timer status register. 11.7 timer 1 during wait mode the cpu clock halts during the wait mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 11.8 timer 1 during stop mode in the stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer flags nor wake up the mcu, but when the mcu does wake up, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. if reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
general release specification mc68hc(7)05cj4 timer 2 motorola rev. 2.1 12-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 12 timer 2 12.1 introduction the timer for this device is a 15-stage multi-functional ripple counter. features include: ? timer over flow (tof) ? real time interrupt (rti) ? computer operating properly (cop) watchdog. as seen in figure 12-1, the timer begins with a fixed divide by four prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer 2 counter register (t2cr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of e/1024. two additional stages produce the por function at e/4064. the timer counter bypass circuitry is at this point in the timer chain. this circuit is followed by two more stages, with the resulting clock (e/16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1-of-4 selector. the output of the rti circuit is further divided by eight to drive the software configurable cop watchdog timer circuit. the rti rate selector bits, and the rti and tof enable bits and flags are located in the timer control and status register at location $08.
general release specification motorola timer 2 mc68hc(7)05cj4 12-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 12-1. timer 2 block diagram 12.2 flag clearing considerations in rare instances, clearing any of the timer 2 control and status register (t2csr) flag or enable bits could result in vectoring to the reset vector rather than the timer interrupt vector if the correct precautions are not followed. do not clear any of the timer flags or enable bits (for example, tof, tofe, rti, and rtif) with bit manipulation instructions. cop clear mc68hc05 internal bus internal 8-bit free $09 7-bit counter tof rtif tofe rtie rt1 interrupt circuit $08 timer running counter rti select circuit counter register status register rt0 processor clock ? ?4 timer control & overflow circuit detect cop watchdog timer (? 8) to reset logic to interrupt logic 8 8
general release specification mc68hc(7)05cj4 timer 2 motorola rev. 2.1 12-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 12.2.1 clearing timer overflow flag (tof) use the following program to clear timer overflow flag (tof) bit. sei sei not required if used within timer interrupt routine lda #$73 and $t2csr or #$40 mask rtif bit sta $t2csr cli do not use cli if this code segment is used within timer interrupt routine 12.2.2 clearing timer overflow flag enable (tofe) use the following program to clear timer overflow flag enable (tofe) bit. sei sei not required if used within timer interrupt routine lda #$d3 and $t2csr or #$c0 mask rtif & tof sta $t2csr cli do not use cli if this code segment is used within timer interrupt routine. masking the real-time interrupt flag (rtif) and timer overflow flag (tof) bits with the or instruction prevents these bits from being cleared if a tof or real time interrupt (rti) is generated during the clearing routine. similar sequences should be used for clearing of the rtif and real-time interrupt enable (rtie) bits.
general release specification motorola timer 2 mc68hc(7)05cj4 12-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 12.3 timer 2 control and status register (t2csr) the t2csr contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. tof timer over flow tof is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if tofe is set. clearing the tof is done by writing a zero to it (tofr). writing a one to tofr has no effect on the bits value. reset clears tof. rtif real time interrupt flag the real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. the clock frequency that drives the rti circuit is e/2**14 (or e/16384) with three additional divider stages giving a maximum interrupt period of 65.5 milliseconds at a bus rate of 2 mhz. rtif is a clearable, read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. a cpu interrupt request will be generated if rtie is set. clearing the rtif is done by writing a zero to it (rtifr). writing a one to rtifr has no effect on this bit. reset clears rtif. note care should be taken when clearing tof and rtif. writing a zero to a bit that is already clear can cause a pending interrupt to be missed. for this reason, the use of a read-modify-write instruction is not recommended. to insure proper operation, only write a logic zero to a flag that is already set and a logic one to any flag that is clear. tofe timer over flow enable when this bit is set, a cpu interrupt request is generated when the tof bit is set. reset clears this bit. bit 7 654321 bit 0 $0013 t1sr read: tof rtif tofe rtie cope irqs rt1 rt0 write: tofr rtifr reset: 00000011 figure 12-2. timer 2 control/status register
general release specification mc68hc(7)05cj4 timer 2 motorola rev. 2.1 12-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 rtie real time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. cope cop enable when set, cope turns on the cop. it can only be written to once after reset. reset clears cope and either a 0 or a 1 can be written to it in order to lock in the desired function. please refer to 12.4 cop watchdog reset for more information on the cop. 1 = cop enabled 0 = cop disabled irqs irq select this bit selects the type of input recognized by the irq interrupt input. it can only be written to once after reset. reset clears irqs and either a 0 or a 1 can be written to it in order to lock in the desired function. 1 = negative edge sensitive only. 0 = negative edge and level sensitive.always read zero rt1:rt0 real time interrupt rate select these two bits select one of four taps from the real time interrupt circuit. table 12-1 shows the available interrupt rates with a 2 mhz bus clock. reset sets these two bits which selects the lowest periodic rate and gives the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. table 12-1. rti and cop rates at 2 mhz bus frequency rt1:rt0 ratio rti rate minimum cop reset 00 e/2 14 8.2 ms 57.4 ms 01 e/2 15 16.4 ms 114.8 ms 10 e/2 16 32.8 ms 229.6 ms 11 e/2 17 65.5 ms 458.5 ms
general release specification motorola timer 2 mc68hc(7)05cj4 12-6 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 12.4 cop watchdog reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 12-1. if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop time-out is done by writing a zero to bit 0 of address $1ff0. when the cop is cleared, only the final divide by eight stage (output of the rti) is cleared. 12.5 timer 2 counter register (t2cr) the timer 2 counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at e divided by 4 and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted anytime during operation (other than por), the counter chain will be cleared. 12.6 timer 2 during wait mode the cpu clock halts during the wait mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 12.7 timer 2 during stop mode the timer is cleared when going into stop mode. when stop is exited by an external interrupt or an external reset, the internal oscillator will resume, followed by a 4064 internal processor oscillator stabilization delay. the timer is then cleared and operation resumes. bit 7 654321 bit 0 $0009 t2cr read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: unaffected by reset figure 12-3. timer 2 counter register
general release specification mc68hc(7)05cj4 instruction set motorola rev. 2.1 13-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 13 instruction set 13.1 introduction this section describes the addressing modes and instruction types. 13.2 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes define the manner in which the cpu finds the data required to execute an instruction. the eight addressing modes are the following: ? inherent ? immediate ? direct ? extended ? indexed, no offset ? indexed, 8-bit offset ? indexed, 16-bit offset ? relative 13.2.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no memory address and are one byte long. 13.2.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte.
general release specification motorola instruction set mc68hc(7)05cj4 13-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13.2.3 direct direct instructions can access any of the first 256 memory addresses with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 13.2.4 extended extended instructions use only three bytes to access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 13.2.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000C$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 13.2.6 indexed, 8-bit offset indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000C$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
general release specification mc68hc(7)05cj4 instruction set motorola rev. 2.1 13-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13.2.7 indexed, 16-bit offset indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing the motorola assembler determines the shortest form of indexed addressing. 13.2.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of C128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
general release specification motorola instruction set mc68hc(7)05cj4 13-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13.3 instruction types the mcu instructions fall into the following five categories: ? register/memory instructions ? read-modify-write instructions ? jump/branch instructions ? bit manipulation instructions ? control instructions 13.3.1 register/memory instructions most of these instructions use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 13-1 lists the register/memory instructions. table 13-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
general release specification mc68hc(7)05cj4 instruction set motorola rev. 2.1 13-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13.3.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 13-2 lists the read-modify-write instructions. 13.3.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump to subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these three-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the conditional branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and table 13-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (ones complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst
general release specification motorola instruction set mc68hc(7)05cj4 13-6 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 its condition (set or clear) is part of the opcode. the span of branching is from C128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 13-3 lists the jump and branch instructions. table 13-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
general release specification mc68hc(7)05cj4 instruction set motorola rev. 2.1 13-7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13.3.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the first 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. bit manipulation instructions use direct addressing. table 13-4 lists these instructions. 13.3.5 control instructions these register reference instructions control cpu operation during program execution. control instructions, listed in table 13-5, use inherent addressing. table 13-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 13-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
general release specification motorola instruction set mc68hc(7)05cj4 13-8 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13.4 instruction set summary table 13-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 13-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 c b0 b7 0 b0 b7 c
general release specification mc68hc(7)05cj4 instruction set motorola rev. 2.1 13-9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff p 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
general release specification motorola instruction set mc68hc(7)05cj4 13-10 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) C (m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? ( ) = $ff C (m) a ? ( ) = $ff C (m) x ? ( ) = $ff C (m) m ? ( ) = $ff C (m) m ? ( ) = $ff C (m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) C (m) 1 imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc m a x m m
general release specification mc68hc(7)05cj4 instruction set motorola rev. 2.1 13-11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc c c d c ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? conditional address dir ext ix2 ix1 ix bd c d d d ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0
general release specification motorola instruction set mc68hc(7)05cj4 13-12 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) dir inh inh ix1 ix 30 40 50 60 70 ii ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 6 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) C (m) C (c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 b0 b7 c
general release specification mc68hc(7)05cj4 instruction set motorola rev. 2.1 13-13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) C (m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) C $00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit not affected table 13-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
motorola instruction set mc68hc(7)05cj4 13-14 rev. 2.1 table 13-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 tax 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
general release specification mc68hc(7)05cj4 electrical specifications motorola rev. 2.1 14-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 14 electrical specifications 14.1 introduction this section contains parametric and timing information. 14.2 maximum ratings note this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for instance, either v ss or v dd ). rating symbol value unit supply voltage v dd C0.3 to +7.0 v input voltage v in v ss C0.3 to v dd +0.3 v bootloader mode ( irq pin only) v tst v ss C0.3 to 2 x v dd +0.3 v current drain per pin excluding v dd and v ss i 12.5 ma storage temperature range t stg -65 to + 150 ? c note: voltages referenced to v ss
general release specification motorola electrical specifications mc68hc(7)05cj4 14-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 14.3 operating temperature range 14.4 thermal characteristics 14.5 power considerations the average chip junction temperature, t j , in ?c can be obtained from: (1) where: t a = ambient temperature in c q ja = package thermal resistance, junction to ambient in c/w p d = p int + p i/o p int = i dd v dd = chip internal power dissipation p i/o = power dissipation on input and output pins (user-determined) for most applications, p i/o p int and can be neglected. ignoring p i/o , the relationship between p d and t j is approximately: (2) solving equations (1) and (2) for k gives: (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . rating symbol value unit operating temperature range mc68hc705cj4 (standard) t a t l to + t h 0 to +70 ? c characteristic symbol value unit thermal resistance 44-lead plastic quad flat pack q ja 170 ? c/w t j t a p d q ja () + = p d k t j 273 c + ------------------------------ = kp d t a 273 c q ja p d + + =
general release specification mc68hc(7)05cj4 electrical specifications motorola rev. 2.1 14-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 14.6 recommended dc operating characteristics 14.7 dc electrical characteristics (1) (4.5 to 5.5 vdc) rating symbol min typ max unit operating voltage f op = 2.1 mhz f op = 1.0 mhz v dd 4.5 3.0 5.0 5.5 5.5 v programming voltage v pp 12.0 12.5 13.0 v note: voltages referenced to v ss = 0 vdc, t a = 25 c characteristic symbol min typ max unit output voltage (i load = 10 m a) (i load = C10.0 m a) v ol v oh v dd C 0.1 0.1 v output high voltage (i oh = C0.8 ma) pa0Cpa7, pb0Cpb7, pc0Cpc7, tcmp v oh v dd C 0.8 v output low voltage (i oh = C1.6 ma) pa0Cpa7, pb0Cpb7, tcmp (i oh = 10 ma) pc0Cpc7 v ol 0.4 0.8 v input high voltage pa0Cpa7, pb0Cpb7, pc0Cpc7, pd0Cpd7, osc1, tcap v ih v dd x 0.7 v dd v input low voltage pa0Cpa7, pb0Cpb7, pc0Cpc7, pd0Cpd7, osc1, tcap v il v ss 0.2 x v dd v supply current (see note 2) run (f op = 2.1 mhz) wait (f op = 2.1 mhz) stop 25 c 0 c to +70 c i dd 7.0 3.0 5.0 10 4 10 20 ma ma m a m a i/o ports hi-z leakage current pa0Cpa7, pb0Cpb7, pc0Cpc7, pd0Cpd7 i oz 1.0 m a input current reset, osc1 i in 1.0 m a capacitance ports (as input or output) reset c out c in 12 8 pf notes: 1. v dd = 4.5 vdc v dd 5.5 vdc, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. reset, irq, sck, tcap, sdio, and sck2 are equipped with schmitt trigger inputs.
general release specification motorola electrical specifications mc68hc(7)05cj4 14-4 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 14.8 dc electrical characteristics (1) (3.0 to 4.5 vdc) characteristic symbol min typ max unit output voltage (i load = 10.0 m a) (i load = C10.0 m a) v ol v oh v dd C 0.1 0.1 v output high voltage (i oh = 0.2 ma) pa0Cpa7, pb0Cpb7, pc0Cpc7, tcmp v oh v dd C 0.3 v output low voltage (i oh = 0.4 ma) pa0Cpa7, pb0Cpb7, tcmp (i oh = 2.5 ma) pc0Cpc7 v ol 0.3 0.6 v input high voltage pa0Cpa7, pb0Cpb7, pc0Cpc7, pd0Cpd7, osc1, tcap v ih v dd x 0.7 v dd v input low voltage pa0Cpa7, pb0Cpb7, pc0Cpc7, pd0Cpd7, osc1, tcap v il v ss 0.2 x v dd v supply current (see note 2) run (f op = 1.0 mhz) wait (f op = 1.0 mhz) stop 25 c 0 c to +70 c i dd 3.0 1.5 3.0 4 2 6 12 ma ma m a m a i/o ports hi-z leakage current pa0Cpa7, pb0Cpb7, pc0Cpc7, pd0Cpd7 i oz 1.0 m a input current reset, osc1 i in 1.0 m a capacitance ports (as input or output) reset c out c in 12 8 pf notes: 1. v dd = 3.0 vdc v dd 4.5 vdc, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. reset, irq, sck, tcap, sdio, and sck2 are equipped with schmitt trigger inputs.
general release specification mc68hc(7)05cj4 electrical specifications motorola rev. 2.1 14-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 14.9 control timing (1) (4.5 to 5.5 vdc) 14.10 control timing (1) (3.0 to 4.5 vdc) characteristic symbol min max unit frequency of operation ( 5%) crystal option square wave signal (external clock source) f osc 4.2 4.2 mhz internal operating frequency (f osc /2) crystal square wave signal f op 2.1 2.1 mhz cycle time (1/f op )t cyc 476 ns reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 100 ns interrupt pulse period t ilil note 2 ns osc1 pulse width t oh , t ol 90 ns notes: 1. v dd = 4.5 vdc v dd 5.5 vdc, t a = 0 c to +70 c, unless otherwise noted 2. the minimum period t ilil should not be less than the number of cycles to execute the interrupt service routine plus 21 t cyc . characteristic symbol min max unit frequency of operation ( 5%) crystal option square wave signal (external clock source) f osc 2.0 2.0 mhz internal operating frequency (f osc /2) crystal square wave signal f op 1.0 1.0 mhz cycle time (1/f op )t cyc 1000 ns reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 200 ns interrupt pulse period t ilil note 2 ns osc1 pulse width t oh , t ol 200 ns notes: 1. v dd = 3.0 vdc v dd 4.5 vdc, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. the minimum period t ilil should not be less than the number of cycles to execute the interrupt service routine plus 21 t cyc .
general release specification mc68hc(7)05cj4 mechanical specifications motorola rev. 2.1 15-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 15 mechanical specifications 15.1 introduction the mc68hc(7)05cj4 is available in a 44-lead quad flat pack (qfp) package. package dimensions for this package were not available at time of this publication. to make sure that you have the latest case outline specifications, contact one of the following: ? local motorola sales office ? motorola mfax C phone 602-244-6609 C email rmfax0@email.sps.mot.com ? worldwide web (wwweb) at http://design-net.com follow mfax or wwweb on-line instructions to retrieve the current mechanical specifications. 15.2 44-lead qfp package at time of publication, the package dimension drawing for the 44-lead qfp package was not available.
general release specification mc68hc(7)05cj4 ordering information motorola rev. 2.1 16-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 section 16 ordering information 16.1 introduction this section contains instructions for ordering custom-masked rom mcus. 16.2 mcu ordering forms to initiate an order for a rom-based mcu, first obtain the current ordering form for the mcu from a motorola representative. submit the following items when ordering mcus: ? a current mcu ordering form that is completely filled out (contact your motorola sales office for assistance.) ? a copy of the customer specification if the customer specification deviates from the motorola specification for the mcu ? customers application program on one of the media listed in 16.3 application program media the current mcu ordering form is also available through the motorola freeware bulletin board service (bbs). the telephone number is (512) 891-free. after making the connection, type bbs in lower-case letters. then press the return key to start the bbs software. 16.3 application program media please deliver the application program to motorola in one of the following media: ? macintosh 1 3 1/2-inch diskette (double-sided 800k or double-sided high-density 1.4m) ? ms-dos 2 or pc-dos tm 3 3 1/2-inch diskette (double-sided 720k or double-sided high-density 1.44m) ? ms-dos or pc-dos tm 5 1/4-inch diskette (double-sided double- density 360k or double-sided high-density 1.2m) 1. macintosh is a registered trademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of international business machines corporation.
general release specification motorola ordering information mc68hc(7)05cj4 16-2 rev. 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 use positive logic for data and addresses. when submitting the application program on a diskette, clearly label the diskette with the following information: ? customer name ? customer part number ? project or product name ? file name of object code ? date ? name of operating system that formatted diskette ? formatted capacity of diskette on diskettes, the application program must be in motorolas s-record format (s1 and s9 records), a character-based object file format generated by m6805 cross assemblers and linkers. note begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom locations or leave all non-user rom locations blank . refer to the current mcu ordering form for additional requirements. motorola may request pattern re-submission if non-user areas contain any non-zero code. if the memory map has two user rom areas with the same address, then write the two areas in separate files on the diskette. label the diskette with both file names. in addition to the object code, a file containing the source code can be included. motorola keeps this code confidential and uses it only to expedite rom pattern generation in case of any difficulty with the object code. label the diskette with the file name of the source code. 16.4 rom program verification the primary use for the on-chip rom is to hold the customers application program. the customer develops and debugs the application program and then submits the mcu order along with the application program.
general release specification mc68hc(7)05cj4 ordering information motorola rev. 2.1 16-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 motorola inputs the customers application program code into a computer program that generates a listing verify file. the listing verify file represents the memory map of the mcu. the listing verify file contains the user rom code and may also contain non-user rom code, such as self-check code. motorola sends the customer a computer printout of the listing verify file along with a listing verify form. to aid the customer in checking the listing verify file, motorola will program the listing verify file into customer-supplied blank preformatted macintosh or dos disks. all original pattern media are filed for contractual purposes and are not returned. check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to motorola. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask. 16.5 rom verification units (rvus) after receiving the signed listing verify form, motorola manufactures a custom photographic mask. the mask contains the customers application program and is used to process silicon wafers. the application program cannot be changed after the manufacture of the mask begins. motorola then produces 10 mcus, called rvus, and sends the rvus to the customer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customers user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for qualification or production. rvus are not guaranteed by motorola quality assurance. 16.6 mc order numbers table 16-1 shows the mc order numbers for the available package types. note: fb = 44-lead quad ?at pack (qfp) package table 16-1. mc order numbers mc order number operating temperature range mc68hc(7)05cj4fb 0 to 70 c
motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?cally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?cers, employees, subsidiaries, af?liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?rmative action employer. how to reach us: mfax: rmfax0@email.sps.mot.com - touchtone (602) 244-6609 internet: http://design-net.com usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 japan: nippon motorola ltd.; tatsumi-spd-jldc, toshikatsu otsuki, 6f seibu-butsuryu-center, 3-14-3 tatsumi koto-ku, tokyo 135, japan. 03-3521-8315 hong kong: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting tok road, tai po, n.t., hong kong. 852-26629298 HC05CJ4GRS/d

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